Tile PD Lead

Drive physical design for large SoC/blocks, from initial concept through tape-out. Own block-level and top-level implementation on advanced nodes (5nm or below), leading synthesis for high-speed designs and execution/optimization of Place & Route. Collaborate with RTL/Logic designers and cross-functional teams to integrate seamlessly and resolve issues. Apply strong low-power understanding (UPF, power-gating, isolation) and use scripting and Unix/Linux environments to debug and optimize results.