ASIC DFT Engineer II Full Time - United States

Cisco
San Jose
Workplace: HybridFull timeFunction: Hardware, Embedded & Systems EngineeringEducation: bachelorsSkills: ["Collaboration","Communication","Debugging","Automation","Verification"]

Design and implement hardware Design-for-Test (DFT) features for ATE, in-system test, debug, and diagnostics in Cisco’s Silicon One organization. Partner with frontend RTL, backend physical design, and verification teams to drive early DFT requirements and integrate/validate test logic through implementation and post-silicon flows. Build automation scripts to improve robustness and efficiency, verify test timing and logic equivalency using SystemVerilog, and use ATPG/EDA tools for pattern generation and analysis.

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FursaFursa
Cisco
Cisco
5 days ago

ASIC DFT Engineer II Full Time - United States

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Last checked: 5 hours agoStatus: Live

Job Summary

Design and implement hardware Design-for-Test (DFT) features for ATE, in-system test, debug, and diagnostics in Cisco’s Silicon One organization. Partner with frontend RTL, backend physical design, and verification teams to drive early DFT requirements and integrate/validate test logic through implementation and post-silicon flows. Build automation scripts to improve robustness and efficiency, verify test timing and logic equivalency using SystemVerilog, and use ATPG/EDA tools for pattern generation and analysis.
Location: San Jose
Workplace: Hybrid
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Implement DFT features that support ATE, in-system test, debug, and diagnostics for ASIC designs.
  • •Create and enhance automation scripts to improve DFT implementation robustness and efficiency.
  • •Work with Design, Design Verification, and Physical Design teams to integrate and validate test logic across implementation and post-silicon validation flows.
  • •Collaborate to validate test timing and logic equivalency of designs using SystemVerilog.
  • •Use ATPG and EDA tools (TestMax, Tetramax, Tessent, PrimeTime) for test pattern generation and analysis.

Pay and Benefits

Equity and Bonus:Equity
Perks:Health InsuranceDentalVision401kParental LeaveDisability

Key Requirements

  • •Meet one of: a Master’s degree with 0 years of experience, or a Bachelor’s degree with 2 years of experience in ASIC Engineering (or related field).
  • •Foundational understanding or exposure to JTAG protocols, scan architectures, and BIST (including memory BIST and boundary scan).
  • •Familiarity with EDA and ATPG tools, plus scripting/coding skills in Python, Tcl, or Perl.
  • •Experience with gate-level simulation and debugging using simulators like VCS.
  • •Preferred: practical verification experience using SystemVerilog, logic equivalency, and test-timing validation.
Education:Bachelor's
Skills:CollaborationCommunicationDebuggingAutomationVerification
Tech Stack:SystemVerilogJTAGScan architectureBISTATP GTestMaxTetramaxTessentPrimeTimePythonTclPerlVCS

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
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