Graduate Talent (Design Verification Engineer)

Develop and execute functional verification plans for PCIe controller IP, ensuring IP logic meets microarchitecture specifications. Build and maintain SystemVerilog-based test benches and verification environments using OOP/OVM/UVM methodologies. Run system simulations to analyze power, timing, and functionality in the pre-silicon stage, debugging and root-causing failing test cases. Collaborate with architects, RTL developers, and physical design teams, and document verification strategies and results.