CPU Architecture and RTL Design Lead Engineer
AMD
Cork
Workplace: HybridFull timeFunction: Architecture & Urban PlanningEducation: bachelorsSkills: ["Verilog","HDL","RTL design","Clocking","Power management","Static Timing","CDC","Static Power analysis","CPU architecture"]Lead the architecture definition, RTL design, and integration of clocking, reset and power for AMD’s next-generation CPUs. Collaborate with a cross-functional team to drive CPL microarchitecture from concept through tapeout, delivering high-performance, power-efficient CPU cores while engaging with verification, physical design, and logic teams.
