IC Design Engineer

Apply and lead physical design methodology and milestone flow to achieve right-first-time silicon. Own block-level and SoC-level layout activities including floorplanning, partitioning, placement, clock tree synthesis, routing, and physical verification. Implement timing and functional ECO, drive P&R/extraction/physical verification work toward STA closure, and build or adapt automation flows. Use and support EDA tools for P&R, PV, STA, and ECO, including Cadence/Synopsys/Mentor, with strong scripting expertise.