Senior Silicon Design Engineer

AMD
Penang
Workplace: HybridFull timeMYR 87,500 - 125,000 annuallyFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Collaboration","Independent decision-making","Communication","Debug analysis","Mentoring"]

Design and integrate front-end ASIC/SoC RTL for complex multi-clock-domain blocks within AMD’s AECG team. Convert chip specifications into synthesizable Verilog RTL, plan and deliver IP-level RTL integration, and optimize for power, performance, area, and timing. Perform lint/CDC, synthesis and LEC flows, write SDC constraints and assertions, and support post-silicon debug while mentoring junior engineers.

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FursaFursa
AMD
AMD
19 hours ago

Senior Silicon Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 13 hours agoStatus: Live

Job Summary

Design and integrate front-end ASIC/SoC RTL for complex multi-clock-domain blocks within AMD’s AECG team. Convert chip specifications into synthesizable Verilog RTL, plan and deliver IP-level RTL integration, and optimize for power, performance, area, and timing. Perform lint/CDC, synthesis and LEC flows, write SDC constraints and assertions, and support post-silicon debug while mentoring junior engineers.
Location: Penang
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Convert chip specifications into RTL using internal and external IPs and implement front-end RTL integration.
  • •Plan and deliver IP-level RTL, including integration of processor-based sub-systems, serial standard interfaces, and memory controllers.
  • •Optimize designs to meet power, performance, area, and timing requirements.
  • •Run unit-level testing and create assertions to improve coverage; write synthesizable Verilog RTL.
  • •Participate in post-silicon functional/performance debug and tuning, and mentor junior engineers.

Pay and Benefits

Salary: MYR 87,500 - 125,000 annually

Key Requirements

  • •Hands-on RTL coding and IP RTL integration for ASIC/SoC front-end design.
  • •Proficiency with Verilog, VHDL, and SystemVerilog, including complex multi-clock-domain block design.
  • •Experience with ASIC/SoC front-end design methodologies and flows (e.g., synthesis and LEC).
  • •Knowledge of quality checks including lint and CDC (including tools like Spyglass) and ability to identify/implement complex ECOs.
  • •Bachelors or Masters degree in computer engineering or electrical engineering.
Experience:ASICSoC
Education:Bachelor's in computer engineering/Electrical Engineering
Skills:CollaborationIndependent decision-makingCommunicationDebug analysisMentoring
Tech Stack:RTLVerilogVHDLSystemVerilogTCLShell scriptPerlPythonSpyglassCDCLintLECSynthesisNetlistECOSDCAssertionsRISC-VNOCDMA

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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