Samsung

4 months ago

Design Technology Co-Optimization (DTCO) Engineer, Design flow and Methodology

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 14 hours agoStatus: Live

Job Summary

DTCO Engineer at Samsung leads the development of design and analysis flows for low-power, high-performance SoC designs, focusing on digital design flows, synthesis, place and route, and PPA optimization. Collaborates with IP teams and foundry partners to ensure DTCO design methodologies scale across large-scale projects with high impact in a production environment.

Location: Austin

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Build CAD flows for DTCO and push PPA envelopes for aggressive designs with automation.
•Develop methodologies for low-power and high-performance goals for Samsung-specific SOC designs.
•Collaborate with IP development teams to ensure design rules and standard cell design changes are consumable across the product development cycle.
•Publish results, maintain thorough documentation, and fulfill project management needs.
•Drive production-level, high-impact, large-scale projects with cross-functional stakeholders.

Pay and Benefits

Salary: USD 180,200 - 270,400 annually

Perks:MedicalDentalVisionLife Insurance401kMeal AllowanceTuition AssistancePaid LeaveStudent LoanWellness Stipend

Key Requirements

•15+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 13+ years of experience with a Master’s Degree, or 11+ years of experience with a Ph.D.
•10+ years of custom design tools and methodology development experience.
•10+ years of experience with industry standard automated design tools for synthesis, place and route, EM/IR analysis, static timing analysis and/or physical verification.
•10+ years of experience working with Cadence Innovus and/or Synopsys Fusion Compiler and reference flows.
•Experience with PPA analysis across standard cell library, memory compiler, interconnect stack options and block-level PPA evaluation.

Experience:15+ yearsSemiconductor

Education:Bachelor's

Skills:CommunicationCollaborationProblem-solvingDocumentationSelf-starterDetail oriented

Languages:English

Tech Stack:Cadence InnovusSynopsys Fusion CompilerSynthesisPlace and routeEM/IRStatic timing analysisPower estimationStandard cell designPythonTclPerl

Company Brief

Samsung

Global conglomerate known for consumer electronics, home appliances, semiconductors, displays, and mobile devices. Designs and manufactures a wide range of products and solutions for consumers, enterprises, and industrial customers worldwide.

Industry: Conglomerates & Holding Companies

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Seoul, South Korea

Founded: 1938

Glassdoor: 3.7

Website LinkedIn

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Samsung

4 months ago

Design Technology Co-Optimization (DTCO) Engineer, Design flow and Methodology

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 14 hours agoStatus: Live

Job Summary

Location: Austin

Workplace: Onsite

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Build CAD flows for DTCO and push PPA envelopes for aggressive designs with automation.
•Develop methodologies for low-power and high-performance goals for Samsung-specific SOC designs.
•Collaborate with IP development teams to ensure design rules and standard cell design changes are consumable across the product development cycle.
•Publish results, maintain thorough documentation, and fulfill project management needs.
•Drive production-level, high-impact, large-scale projects with cross-functional stakeholders.

Pay and Benefits

Salary: USD 180,200 - 270,400 annually

Perks:MedicalDentalVisionLife Insurance401kMeal AllowanceTuition AssistancePaid LeaveStudent LoanWellness Stipend

Key Requirements

•15+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 13+ years of experience with a Master’s Degree, or 11+ years of experience with a Ph.D.
•10+ years of custom design tools and methodology development experience.
•10+ years of experience with industry standard automated design tools for synthesis, place and route, EM/IR analysis, static timing analysis and/or physical verification.
•10+ years of experience working with Cadence Innovus and/or Synopsys Fusion Compiler and reference flows.
•Experience with PPA analysis across standard cell library, memory compiler, interconnect stack options and block-level PPA evaluation.

Experience:15+ yearsSemiconductor

Education:Bachelor's

Skills:CommunicationCollaborationProblem-solvingDocumentationSelf-starterDetail oriented

Languages:English

Tech Stack:Cadence InnovusSynopsys Fusion CompilerSynthesisPlace and routeEM/IRStatic timing analysisPower estimationStandard cell designPythonTclPerl

Company Brief

Samsung

Industry: Conglomerates & Holding Companies

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Seoul, South Korea

Founded: 1938

Glassdoor: 3.7

Website LinkedIn