FPGA Verification Engineer, Air Dominance and Strike

Anduril
United States
Workplace: OnsiteFull timeUSD 146,000 - 194,000 annuallyFunction: Hardware, Embedded & Systems EngineeringExperience: 2+ yearsEducation: bachelorsSkills: ["Communication","Teamwork"]

Own FPGA/SoC verification for flight-critical avionics on AMD (Xilinx) platforms, building UVM-based, coverage-driven verification environments. Create verification plans with traceability, develop SVA for protocol and design intent checks, and drive constrained-random transaction sequences to uncover corner cases. Maintain regression suites, analyze coverage to closure, and debug failures using waveform tools and simulation logs while collaborating with RTL/design teams and supporting board bring-up and DO-254-aligned verification.

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Anduril
Anduril
1 day ago

FPGA Verification Engineer, Air Dominance and Strike

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Last checked: 11 minutes agoStatus: Live
Reposted: similar role first listed 4 months ago

Job Summary

Own FPGA/SoC verification for flight-critical avionics on AMD (Xilinx) platforms, building UVM-based, coverage-driven verification environments. Create verification plans with traceability, develop SVA for protocol and design intent checks, and drive constrained-random transaction sequences to uncover corner cases. Maintain regression suites, analyze coverage to closure, and debug failures using waveform tools and simulation logs while collaborating with RTL/design teams and supporting board bring-up and DO-254-aligned verification.
Location: United States
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Architect and implement UVM verification environments for AMD (Xilinx) FPGA/SoC designs.
  • •Develop verification plans with traceability to system and hardware requirements.
  • •Author SVA for protocol compliance and design intent checks.
  • •Build functional coverage models and drive code coverage analysis to closure using regression suites.
  • •Debug simulation failures using waveform tools and simulation logs, and collaborate with design engineers on RTL reviews and bug resolution.

Pay and Benefits

Salary: USD 146,000 - 194,000 annually

Key Requirements

  • •Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
  • •2+ years of experience in FPGA/ASIC verification.
  • •Proficiency in SystemVerilog, UVM methodology, and SVA; experience contributing to and extending UVM testbenches.
  • •Experience with verification environments and building coverage-driven verification (functional coverage, regression suites).
  • •Eligible to obtain and hold a U.S. Secret security clearance.
Experience:2+ yearsFPGA verificationASIC verificationAvionicsUVM
Education:Bachelor's in Electrical Engineering, Computer Engineering, or related field
Skills:CommunicationTeamwork
Tech Stack:FPGASoCAMD (Xilinx)SystemVerilogUVMSVAUVM testbenchesFunctional coverageConstrained-randomTransaction-level testingQuestaVCSXceliumVivadoGitLinuxPythonTclMakefileSVUnit

Eligibility

Security Clearance:Secret

Company Brief

Anduril
Designs and builds advanced defense systems combining autonomous aircraft, sensors, and AI-driven software for military and national security applications, focused on modernizing battlefield capabilities and distributed sensing.
Industry: Defense Technology
Company Size: Enterprise (1,001+ employees)
Growth: Scaleup
Valuation: Unicorn (USD 1B+)
Funding: Series E+
Headquarters: Costa Mesa, United States
Founded: 2017
WebsiteLinkedIn