SR Engineer, ASIC DFT

Micron Technology
Hyderabad
Workplace: OnsiteFull timeFunction: Hardware, Embedded & Systems EngineeringExperience: 5+ yearsEducation: bachelorsSkills: ["Communication","Time management","Multi-tasking","Collaboration"]

Implement DFT for Micron IPs and memory controllers, supporting early analysis through silicon bring-up and characterization. Own innovative scan, MBIST, LBIST, and boundary scan insertion at RTL and gate level, generate and validate ATPG patterns via simulation, and verify DFT using RTL and gate-level simulations. Collaborate cross-functionally with STA, synthesis, LEC, CLP, verification, and validation teams, and contribute to overall DFT methodology development.

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FursaFursa
Micron Technology
Micron Technology
2 months ago

SR Engineer, ASIC DFT

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Source: Company careers pageValidated by: Fursa AI
Last checked: 20 hours agoStatus: Live

Job Summary

Implement DFT for Micron IPs and memory controllers, supporting early analysis through silicon bring-up and characterization. Own innovative scan, MBIST, LBIST, and boundary scan insertion at RTL and gate level, generate and validate ATPG patterns via simulation, and verify DFT using RTL and gate-level simulations. Collaborate cross-functionally with STA, synthesis, LEC, CLP, verification, and validation teams, and contribute to overall DFT methodology development.
Location: Hyderabad
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Accountable for innovative DFT implementation (scan, MBIST, LBIST, and boundary scan) at RTL and gate level for a given SOC at hard macro and chip top level.
  • •Generate and validate ATPG patterns using simulations.
  • •Validate the DFT implementation using RTL and gate-level simulation.
  • •Collaborate with multi-functional teams on STA, synthesis, LEC, CLP, verification, and validation.
  • •Support silicon bring-up activities to ensure the highest stability of test patterns/programs and contribute to overall DFT methodology development.

Pay and Benefits

Perks:Paid LeaveHealth Insurance

Key Requirements

  • •Bachelor’s or Master’s degree (or equivalent experience) in Electronics Engineering, Microelectronics, Software Engineering, or a related field.
  • •5+ years of industry experience in DFT for highly sophisticated SOCs.
  • •Core DFT skills including scan codec insertion, Memory BIST and Repair, Logic BIST, ATPG, BSCAN & JTAG (IEEE1149.1 & IEEE1687), and fault simulation/modeling.
  • •Experience with ATPG fault models and SDF annotated gate-level verification, including scan and memory diagnosis.
  • •Hands-on DFT tool experience with Siemens, Synopsys and/or Cadence, and coding with Verilog, VHDL, C/C++, TCL, Perl, or Python.
Experience:5+ yearsASICSemiconductors
Education:Bachelor's in Electronics Engineering, Microelectronics
Skills:CommunicationTime managementMulti-taskingCollaboration
Tech Stack:ASIC DFTScan CodecMemory BISTLogic BISTATPGBSCANJTAGIEEE1149.1IEEE1687Fault SimulationSAFTDFSDDPDTSDFSiemensSynopsysCadenceVerilogVHDL

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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