ASIC DFT Engineer || DFT/ATPG/MBIST/SCAN/JTAG || 8+ years

Cisco
Bengaluru
Workplace: HybridFull timeFunction: Hardware, Embedded & Systems EngineeringExperience: 8-10 yearsEducation: bachelorsSkills: ["Debugging","Verbal communication","Problem-solving"]

Join the Cisco Silicon One team to implement and evolve hardware Design-for-Test (DFT) features that enable ATE support, in-system testing, debug, and diagnostics. Develop innovative DFT IP, collaborate with RTL and design/verification teams to integrate testability logic across full-chip flows, and support post-silicon validation. You’ll use JTAG, scan insertion, ATPG, and EDA tools while crafting and debugging solutions with minimal mentorship.

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FursaFursa
Cisco
Cisco
1 month ago

ASIC DFT Engineer || DFT/ATPG/MBIST/SCAN/JTAG || 8+ years

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Source: Company careers pageValidated by: Fursa AI
Last checked: 10 hours agoStatus: Live
Reposted: similar role first listed 3 months ago

Job Summary

Join the Cisco Silicon One team to implement and evolve hardware Design-for-Test (DFT) features that enable ATE support, in-system testing, debug, and diagnostics. Develop innovative DFT IP, collaborate with RTL and design/verification teams to integrate testability logic across full-chip flows, and support post-silicon validation. You’ll use JTAG, scan insertion, ATPG, and EDA tools while crafting and debugging solutions with minimal mentorship.
Location: Bengaluru
Workplace: Hybrid
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Implement Hardware Design-for-Test (DFT) features supporting ATE, in-system test, debug, and diagnostics needs.
  • •Develop innovative DFT IP and coordinate testability features for full-chip design integration in RTL.
  • •Collaborate with design, design-verification, and PD teams to integrate and validate test logic across implementation and post-silicon flows.
  • •Craft solutions and debug with minimal mentorship to resolve testability and validation challenges.
  • •Drive ASIC DFT hardware engineering activities using relevant test and simulation technologies.

Key Requirements

  • •Bachelor’s or Master’s degree in Electrical or Computer Engineering with 8–10 years of experience.
  • •Experience with JTAG protocols, scan insertion, and ATPG.
  • •Experience with ATPG and EDA tools such as TestMax, Tetramax, and Tessent.
  • •Experience with gate-level simulation and debugging using VCS and other simulators.
  • •Post-silicon validation and debug experience, including working with ATE patterns and P1687.
Experience:8-10 years
Education:Bachelor's in Electrical or Computer Engineering
Skills:DebuggingVerbal communicationProblem-solving
Tech Stack:JTAGScan insertionATPGTestMaxTetramaxTessentVCSGate-level simulationTclPythonPerlATE patternsP1687

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
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