8 hours ago

DFT Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 8 hours agoStatus: Live

Job Summary

Design, implement, validate, and debug Design-for-Test (DFT) solutions to improve manufacturability, test coverage, and silicon quality across IP and SoC programs. Develop and validate TAP/JTAG and IJTAG infrastructure, boundary scan, MBIST, scan/ATPG methodologies, and related collateral. Perform RTL and gate-level simulation validation, drive coverage optimization, and resolve DFT failures through debug and technical reviews with cross-functional hardware and test teams.

Location: Bengaluru

Workplace: Hybrid

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Design, implement, validate, and debug DFT solutions to ensure manufacturability, test coverage, and silicon quality across IP and SoC programs.
•Develop and validate TAP/JTAG and IJTAG infrastructures, boundary scan (BSCAN), MBIST, scan/ATPG methodologies, and associated test collateral including ICL, PDL, BSDL, and ATPG patterns.
•Drive test access, pattern generation, coverage optimization, and memory test validation across the product lifecycle.
•Perform RTL and gate-level simulation (GLS) validation and conduct root-cause analysis and resolution of DFT-related failures.
•Collaborate with Design, Verification, Physical Design, Product Engineering, Manufacturing Test, and IP teams to ensure DFT readiness, signoff, and continuous process improvements.

Key Requirements

•Bachelor’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or related field with 10+ years of experience OR Master’s degree in Electrical Engineering, Microelectronics, VLSI or related field with 8+ years of experience.
•Experience with scan insertion and DFT features, including RTL design for DFT and verification.
•Experience developing and validating TAP/JTAG and IJTAG infrastructure.
•Experience with Boundary Scan (BSCAN), MBIST, scan/ATPG methodologies, and associated test collateral (ICL, PDL, BSDL, ATPG patterns).
•Strong DFT verification and silicon debug skills, including RTL and gate-level simulation (GLS) validation and root-cause analysis of DFT failures.

Experience:8+ years

Education:

Skills:CommunicationTechnical leadershipRoot-cause analysisDebuggingTechnical reviews

Tech Stack:Design-for-Test (DFT)TAP/JTAGIJTAGIEEE 1687Boundary Scan (BSCAN)IEEE 1149.1MBISTScan/ATPGScan CompressionATPGICLPDLBSDLTclPerlPythonVerilogSystem VerilogRTLGate-Level Simulation (GLS)

Company Brief

Intel

Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1968

Glassdoor: 3.8

Website LinkedIn Glassdoor

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Intel

8 hours ago

DFT Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 8 hours agoStatus: Live

Job Summary

Location: Bengaluru

Workplace: Hybrid

Employment Type: Full time

Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

•Design, implement, validate, and debug DFT solutions to ensure manufacturability, test coverage, and silicon quality across IP and SoC programs.
•Develop and validate TAP/JTAG and IJTAG infrastructures, boundary scan (BSCAN), MBIST, scan/ATPG methodologies, and associated test collateral including ICL, PDL, BSDL, and ATPG patterns.
•Drive test access, pattern generation, coverage optimization, and memory test validation across the product lifecycle.
•Perform RTL and gate-level simulation (GLS) validation and conduct root-cause analysis and resolution of DFT-related failures.
•Collaborate with Design, Verification, Physical Design, Product Engineering, Manufacturing Test, and IP teams to ensure DFT readiness, signoff, and continuous process improvements.

Key Requirements

•Bachelor’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or related field with 10+ years of experience OR Master’s degree in Electrical Engineering, Microelectronics, VLSI or related field with 8+ years of experience.
•Experience with scan insertion and DFT features, including RTL design for DFT and verification.
•Experience developing and validating TAP/JTAG and IJTAG infrastructure.
•Experience with Boundary Scan (BSCAN), MBIST, scan/ATPG methodologies, and associated test collateral (ICL, PDL, BSDL, ATPG patterns).
•Strong DFT verification and silicon debug skills, including RTL and gate-level simulation (GLS) validation and root-cause analysis of DFT failures.

Experience:8+ years

Education:

Skills:CommunicationTechnical leadershipRoot-cause analysisDebuggingTechnical reviews

Tech Stack:Design-for-Test (DFT)TAP/JTAGIJTAGIEEE 1687Boundary Scan (BSCAN)IEEE 1149.1MBISTScan/ATPGScan CompressionATPGICLPDLBSDLTclPerlPythonVerilogSystem VerilogRTLGate-Level Simulation (GLS)

Company Brief

Intel

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1968

Glassdoor: 3.8

Website LinkedIn Glassdoor