Qubit Control Physical Design Engineer

Intel
Oregon
Workplace: HybridFull timeUSD 141,910 - 269,100 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 6+ yearsEducation: bachelorsSkills: ["Debugging","Collaboration","Workflow improvement","Mentorship"]

Own RTL-to-GDS physical design execution for advanced semiconductor technologies, driving RTL convergence and block-level closure to meet power, performance, and area (PPA) goals. You’ll perform floorplanning, placement, power/clock distribution, congestion and timing closure, physical verification, and sign-off. Collaborate with CAD and methodology teams, debug silicon-critical issues (timing, EM/IR, LVS/DRC), and work with custom IP teams to optimize memory macros and standard cell libraries.

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FursaFursa
Intel
Intel
1 day ago

Qubit Control Physical Design Engineer

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Job Summary

Own RTL-to-GDS physical design execution for advanced semiconductor technologies, driving RTL convergence and block-level closure to meet power, performance, and area (PPA) goals. You’ll perform floorplanning, placement, power/clock distribution, congestion and timing closure, physical verification, and sign-off. Collaborate with CAD and methodology teams, debug silicon-critical issues (timing, EM/IR, LVS/DRC), and work with custom IP teams to optimize memory macros and standard cell libraries.
Location: Oregon
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Drive RTL-to-GDS design convergence using synthesis and place-and-route to hit performance, power, and area (PPA) targets.
  • •Deliver block-level physical design closure, including backend flow closure, electrical requirements, and improving silicon yield.
  • •Execute physical implementation tasks such as floor planning, bus/pin placement, power/clock distribution, congestion analysis, timing closure, IR drop analysis, and physical verification.
  • •Debug timing, EM/IR, LVS, and DRC violations and lead sign-off activities for high-quality silicon production.
  • •Collaborate with custom IP teams to define and optimize memory macros and standard cell libraries; develop and refine physical design methodologies.

Pay and Benefits

Salary: USD 141,910 - 269,100 annually
Perks:Health InsuranceRetirementPaid Leave

Key Requirements

  • •Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field plus 6+ years of physical design experience, or a Master's plus 4+ years.
  • •Experience with floor planning, defining timing constraints, synthesis, place-and-route, and achieving product KPIs.
  • •Proficiency in scripting (Python, Perl, TCL) for automation and debugging.
  • •Hands-on debugging of FEV and RV reports, including planning/implementing ECOs.
  • •Strong understanding of chiplet integration and advanced packaging techniques.
Experience:6+ yearsSemiconductor designPhysical design
Education:Bachelor's in Electrical Engineering, Computer Engineering, or a related field
Skills:DebuggingCollaborationWorkflow improvementMentorship
Tech Stack:PythonPerlTCLCadence VirtuosoSynopsys Fusion CompilerJavaC++SerDesUCIe

Company Brief

Intel
Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1968
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