Silicon Design Verification Staff Engineer

AMD
Penang
Workplace: HybridFull timeMYR 235,200 - 336,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 8+ yearsEducation: mastersSkills: ["Communication","Technical discussion","Team leadership","Vocal communication"]

Own IP-level design verification for PCIe SubSystem, partnering with Design and Architecture teams to build and evolve verification infrastructure, components, and environments. Plan and drive verification for new PCIe SS features through verification closure, leveraging ASIC tape-out experience and robust testbench architecture. Contribute to advanced verification methods using UVM and SystemVerilog, with added advantage from PCIe, SerDes PHY, low-power, and formal verification knowledge.

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FursaFursa
AMD
AMD
13 hours ago

Silicon Design Verification Staff Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 2 hours agoStatus: Live

Job Summary

Own IP-level design verification for PCIe SubSystem, partnering with Design and Architecture teams to build and evolve verification infrastructure, components, and environments. Plan and drive verification for new PCIe SS features through verification closure, leveraging ASIC tape-out experience and robust testbench architecture. Contribute to advanced verification methods using UVM and SystemVerilog, with added advantage from PCIe, SerDes PHY, low-power, and formal verification knowledge.
Location: Penang
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Develop and update infrastructure and environment for IP level design verification.
  • •Collaborate with Design and Architecture teams to develop new verification components.
  • •Own verification plan and drive verification closure for PCIe SS new features.

Pay and Benefits

Salary: MYR 235,200 - 336,000 annually

Key Requirements

  • •Solid background with ASIC design verification flow and multiple ASIC tape out experience with 8+ years.
  • •Team leading experience and experience on testbench architecture.
  • •Solid knowledge of UVM, SystemVerilog, and Verilog.
  • •Solid background on PCIe (other high speed IO protocol or SerDes PHY is a big plus).
  • •Experience with low power verification is a plus; knowledge of formal verification is a plus.
Experience:8+ yearsASIC verificationPCIeHigh-speed I/OSerDesUVM
Education:Master's
Skills:CommunicationTechnical discussionTeam leadershipVocal communication
Languages:English
Tech Stack:PCIeUVMSystemVerilogVerilogASICSoCSerDes PHYTestbench architectureFormal verificationLow power verificationHigh speed IO protocol

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
WebsiteLinkedIn