Principal Design Engineer

Cadence Design Systems
Bengaluru, Noida
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 8+ yearsEducation: bachelorsSkills: []

Lead design verification activities for complex VLSI designs, driving SV/UVM-based verification, environment planning, and test plan development. Manage verification environments and code in SystemVerilog, contributing to verification closure and IP verification initiatives, with exposure to memory IPs such as DDR/HBM/GDDR.

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Cadence Design Systems
Cadence Design Systems
7 months ago

Principal Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 3 hours agoStatus: Live

Job Summary

Lead design verification activities for complex VLSI designs, driving SV/UVM-based verification, environment planning, and test plan development. Manage verification environments and code in SystemVerilog, contributing to verification closure and IP verification initiatives, with exposure to memory IPs such as DDR/HBM/GDDR.
Location: Bengaluru, Noida
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Sr. Manager level

Key Responsibilities

  • •Lead design verification activities for complex designs, including plan and execution of verification strategies.
  • •Develop and maintain verification environments using SystemVerilog/UVM and related methodologies.
  • •Create and execute test plans, coordinate with design teams, and drive verification closure for projects.
  • •Verify IPs and memory interfaces (DDR/HBM/GDDR) and assess integration with broader blocks.
  • •Mentor and collaborate with other verification engineers to improve processes and coverage.

Key Requirements

  • •BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.
  • •8+ years of Design Verification experience with SV/UVM
  • •Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.
  • •Design Verification experience verifying complex designs and leading projects from concept to verification closure.
  • •Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required.
Experience:8+ yearsSemiconductorsVLSIIP verificationMemory IPDDRHBMGDDR
Education:Bachelor's in Electrical / Electronics / VLSI
Tech Stack:SystemVerilogUVMSVMemory IPDDRHBMGDDR

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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