Principal Design Engineer

Cadence Design Systems
Seoul
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 9+ yearsSkills: ["Floorplanning","Place and route","Clock tree synthesis","Timing closure","Power integrity","Signal integrity","DRC","LVS","Antenna","EM/IR","DFM","P&R","Verification","Tapeout"]

Seeking a highly experienced Application/Physical Design Engineer focused on ASIC physical design implementation. You will perform floorplanning, place-and-route, clock tree synthesis, timing closure, SI/PI signoff, DRC/LVS/antenna checks, EM/IR signoff, DFM, and contribute to next-generation design methodology and flow development for advanced nodes in Cadence Korea.

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FursaFursa
Cadence Design Systems
Cadence Design Systems
4 months ago

Principal Design Engineer

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Last checked: 17 hours agoStatus: Live

Job Summary

Seeking a highly experienced Application/Physical Design Engineer focused on ASIC physical design implementation. You will perform floorplanning, place-and-route, clock tree synthesis, timing closure, SI/PI signoff, DRC/LVS/antenna checks, EM/IR signoff, DFM, and contribute to next-generation design methodology and flow development for advanced nodes in Cadence Korea.
Location: Seoul
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Perform physical design implementation tasks including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.
  • •Contribute to development and optimization of next-generation physical design methodologies and flows.
  • •Collaborate with RTL design teams to ensure successful tapeouts on challenging CMOS technologies.
  • •Work on low power and high-speed designs at advanced technology nodes.
  • •Take ownership of a variety of technical tasks and work independently when needed.

Key Requirements

  • •9+ years of experience with ASIC design flow, hierarchical physical design strategies, and deep sub-micron technology issues.
  • •Strong knowledge of Low Power Design, DFT, static timing analysis and closure, data skew balancing, duty cycle adjustment, EM/IR-Drop/crosstalk analysis, formal verification, physical verification, DFM and P&R.
  • •Able to assume responsibility for a variety of technical tasks and to work independently.
  • •Hands-on at all levels of design, with the ability to verify, test, and characterize own designs.
  • •Excellent English communication and teamwork to work with RTL design teams for tapeouts.
Experience:9+ yearsSemiconductorASICLow power design
Skills:FloorplanningPlace and routeClock tree synthesisTiming closurePower integritySignal integrityDRCLVSAntennaEM/IRDFMP&RVerificationTapeout
Languages:English
Tech Stack:ASICDFTSTADRCLVSAntennaDFMP&RClock tree synthesisEM/IR

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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