Sr. RTL Design Engineer (Silicon Engineering)
SpaceX
Redmond, Irvine, Austin, Sunnyvale
Workplace: OnsiteFull timeUSD 160,000 - 225,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: bachelorsSkills: ["Verilog","SystemVerilog","RTL","HDL","Python","EDA tools","Synthesis"]Develop cutting-edge RTL for next-generation ASICs used in SpaceX Starlink infrastructure, collaborating with cross-disciplinary teams to optimize timing, power, and integration of RTL across multiple IPs, with hands-on involvement from architecture through silicon bring-up and validation.

