Sr. RTL Design Engineer (Silicon Engineering)

SpaceX
Redmond, Irvine, Austin, Sunnyvale
Workplace: OnsiteFull timeUSD 160,000 - 225,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: bachelorsSkills: ["Verilog","SystemVerilog","RTL","HDL","Python","EDA tools","Synthesis"]

Develop cutting-edge RTL for next-generation ASICs used in SpaceX Starlink infrastructure, collaborating with cross-disciplinary teams to optimize timing, power, and integration of RTL across multiple IPs, with hands-on involvement from architecture through silicon bring-up and validation.

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FursaFursa
SpaceX
SpaceX
3 months ago

Sr. RTL Design Engineer (Silicon Engineering)

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Source: Company careers pageValidated by: Fursa AI
Last checked: 11 hours agoStatus: Live

Job Summary

Develop cutting-edge RTL for next-generation ASICs used in SpaceX Starlink infrastructure, collaborating with cross-disciplinary teams to optimize timing, power, and integration of RTL across multiple IPs, with hands-on involvement from architecture through silicon bring-up and validation.
Location: Redmond, Irvine, Austin, Sunnyvale
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Evaluate architectural trade-offs based on features, performance requirements and system limitations
  • •Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design
  • •Work closely with verification team to ensure all aspects of the design are covered and verified
  • •Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check)
  • •Participate in silicon bring-up and validation

Pay and Benefits

Salary: USD 160,000 - 225,000 annually
Equity and Bonus:Equity
Perks:Health InsuranceVision401kDisabilityPaid ParentalPaid LeaveLife InsuranceDental

Key Requirements

  • •Bachelor’s degree in electrical engineering, computer engineering, or computer science
  • •5+ years of experience in RTL implementation
  • •Ability to solve complex problems including clock domain crossings and power optimization
  • •ASIC/SoC system integration experience
  • •Experience with embedded CPU subsystems
Experience:5+ yearsSpaceAerospaceSatelliteTelecommunications
Education:Bachelor's
Skills:VerilogSystemVerilogRTLHDLPythonEDA toolsSynthesis
Languages:English
Tech Stack:VerilogSystemVerilogAXIAHBHDL simulatorsHDL LintPython

Eligibility

Nationality:US National
Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

SpaceX
Designs, manufactures, and launches advanced rockets and spacecraft for commercial and government customers, aiming to reduce space transportation costs and enable human life on Mars through reusable launch vehicles and integrated space systems.
Industry: Aerospace Manufacturing
Company Size: Enterprise (1,001+ employees)
Growth: Established Company
Valuation: Hectocorn (USD 100B+)
Funding: Series E+
Headquarters: Hawthorne, United States
Founded: 2002
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