SDC, Synthesis and STA Engineer

AMD
Bengaluru
Workplace: OnsiteFull timeINR 3,338,160 - 4,768,800 annuallyFunction: Hardware, Embedded & Systems EngineeringExperience: 6+ yearsEducation: bachelorsSkills: ["Debugging","Technical guidance","Collaboration","Planning","Issue resolution"]

Own the front-end implementation and closure of IPs by planning and executing SDC development, generation, verification, promotion/demotion, and equivalence checking. Work across SDC/constraints flows and may extend into synthesis, LEC, CLP, prelayout STA, and postlayout STA/timing closure. Coordinate with design and PNR teams, guide technical issue debugging, and ensure quality delivery for synthesis and timing closure, including low-power and DFT considerations.

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FursaFursa
AMD
AMD
1 week ago

SDC, Synthesis and STA Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 51 minutes agoStatus: Live
Reposted: similar role first listed 8 months ago

Job Summary

Own the front-end implementation and closure of IPs by planning and executing SDC development, generation, verification, promotion/demotion, and equivalence checking. Work across SDC/constraints flows and may extend into synthesis, LEC, CLP, prelayout STA, and postlayout STA/timing closure. Coordinate with design and PNR teams, guide technical issue debugging, and ensure quality delivery for synthesis and timing closure, including low-power and DFT considerations.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Hardware, Embedded & Systems Engineering
Seniority: Mid level

Key Responsibilities

  • •Plan and execute front-end implementation of IPs and closure, including SDC development and IP closure ownership.
  • •Own SDC generation, verification, promotion/demotion, and equivalence checking using third-party or self-built tools.
  • •Perform additional front-end tasks as needed, including synthesis, LEC, CLP, prelayout STA, and postlayout STA/timing closure.
  • •Coordinate with design and PNR teams to achieve closure and guide team members on technical issues.
  • •Understand required duration, plan execution to schedule, and complete quality delivery for synthesis and timing closure.

Pay and Benefits

Salary: INR 3,338,160 - 4,768,800 annually

Key Requirements

  • •8+ years with a Bachelor’s degree or 6+ years with a Master’s degree in Electrical Engineering.
  • •Experience developing SDC/constraints, with or without tools such as fisthail, excellicon, or TCM.
  • •Experience in synthesis, LEC, CLP, and timing closure.
  • •Knowledge of timing constraints, low power aspects, and DFT concepts.
  • •Debug experience to resolve technical issues.
Experience:6+ years
Education:Bachelor's in Electrical Engineering
Skills:DebuggingTechnical guidanceCollaborationPlanningIssue resolution
Languages:En-us
Tech Stack:SDCSynthesisSTATiming closureLECCLPPrelayout STAPostlayout STAEquivalence checkingRTLNetlistStatic checksLintCDCConstraints developmentLow powerDFTAutomationScriptingFisthail

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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Glassdoor: 3.9
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