ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)
Cisco
Pune, India
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 3+ yearsEducation: bachelorsSkills: ["UVM","Verilog","SystemVerilog","Python","C","RTL","DFT","SPI","I2C","SerDes","Ethernet","Linux","Testbench"]Lead hands-on verification for Cisco’s silicon photonics driver ICs, developing testbenches, UVM-based verification environments, and test plans across block and full-chip levels, coordinating with cross-functional teams to ensure coverage and reliability from concept to production.
