Sr. Fellow -- Memory PHY Architect

AMD
Santa Clara
Workplace: OnsiteFull timeFunction: Architecture & Urban PlanningExperience: 15+ yearsEducation: mastersSkills: ["Memory PHY","High-speed I/O","DDR","LPDDR","GDDR","HBM","CMOS","Analog","Mixed-signal design"]

Lead architect shaping memory PHY technology across DDR, LPDDR, GDDR, and HBM; define architectures and specifications, drive high-speed I/O circuit design, power integrity and signal integrity, and support post-silicon validation. Collaborate with Circuit Design, Layout, Logic Design, Physical Design, Firmware, Design Verification and Post-Silicon teams; mentor engineers and influence long-range roadmaps from Santa Clara, CA.

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FursaFursa
AMD
AMD
8 months ago

Sr. Fellow -- Memory PHY Architect

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Last checked: 12 hours agoStatus: Live

Job Summary

Lead architect shaping memory PHY technology across DDR, LPDDR, GDDR, and HBM; define architectures and specifications, drive high-speed I/O circuit design, power integrity and signal integrity, and support post-silicon validation. Collaborate with Circuit Design, Layout, Logic Design, Physical Design, Firmware, Design Verification and Post-Silicon teams; mentor engineers and influence long-range roadmaps from Santa Clara, CA.
Location: Santa Clara
Workplace: Onsite
Employment Type: Full time
Job Function: Architecture & Urban Planning
Seniority: Director level

Key Responsibilities

  • •Serve as a senior technical authority and architect for Memory PHY technology, shaping long-range roadmaps and architectural direction.
  • •Define and evolve architectures and specifications for advanced Memory PHYs, including DDR, LPDDR, GDDR, and HBM.
  • •Drive innovation in high-speed I/O circuit design, system-level analysis, power integrity, and signal integrity.
  • •Partner with cross-functional teams across Circuit Design, Layout, Logic Design, Physical Design, Firmware, Design Verification, and Post-Silicon organizations worldwide.
  • •Influence design quality and execution through design reviews, technical mentorship, and principled tradeoff decisions.

Key Requirements

  • •15+ years of experience in high-speed analog, mixed-signal, or memory PHY design
  • •Advanced degree in Electrical Engineering or related field preferred
  • •Sustained technical impact on production Memory PHYs or high-speed I/O IP at advanced technology nodes
  • •Experience owning or shaping architecture across multiple successful tape-outs
  • •Deep expertise in high-speed analog and mixed-signal design, memory protocols, and system-level considerations
Experience:15+ yearsMemory PHYHigh-speed I/OCMOSMixed-signalMemory protocols
Education:Master's in Electrical Engineering
Skills:Memory PHYHigh-speed I/ODDRLPDDRGDDRHBMCMOSAnalogMixed-signal design
Languages:English
Tech Stack:Memory PHYDDRLPDDRGDDRHBMHigh-speed I/OCMOSAnalogMixed-signal

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
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