Principal Silicon Design Engineer

AMD
Penang
Workplace: HybridFull timeMYR 235,200 - 336,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 8+ yearsEducation: bachelorsSkills: ["Analytical skills","Communication","Problem-solving","Multi-tasking","Attention to detail"]

Own critical GPU physical-design units and drive RTL-to-GDSII convergence for AMD’s MI/Navi GPU products. Perform feasibility studies using micro-architecture knowledge and optimize PPA tradeoffs. Develop and tailor physical-design methodologies across implementation steps, implementing floorplanning, synthesis, place & route, timing closure, verification (DRC/LVS), and EM/IR/signoff. Use tools such as Synopsys Fusion Compiler, Cadence, PrimeTime, StarRC, Calibre, and Apache Redhawk.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
AMD
AMD
21 hours ago

Principal Silicon Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 13 hours agoStatus: Live
Reposted: similar role first listed 6 months ago

Job Summary

Own critical GPU physical-design units and drive RTL-to-GDSII convergence for AMD’s MI/Navi GPU products. Perform feasibility studies using micro-architecture knowledge and optimize PPA tradeoffs. Develop and tailor physical-design methodologies across implementation steps, implementing floorplanning, synthesis, place & route, timing closure, verification (DRC/LVS), and EM/IR/signoff. Use tools such as Synopsys Fusion Compiler, Cadence, PrimeTime, StarRC, Calibre, and Apache Redhawk.
Location: Penang
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Own critical GPU units and drive convergence from RTL-to-GDSII through synthesis, floor-planning, place and route, timing closure, and signoff.
  • •Perform feasibility studies using micro-architecture knowledge and evaluate performance, power, and area (PPA) tradeoffs for design closure.
  • •Develop and improve physical design methodologies and customize recipes across implementation steps to optimize PPA.
  • •Implement floor plan, synthesis, placement, CTS, timing closure, routing, extraction, and physical verification (DRC & LVS), including EM/IR and signoff.
  • •Handle different PNR tools (Synopsys Fusion Compiler, Cadence, PrimeTime, StarRC, Calibre, Apache Redhawk).

Pay and Benefits

Salary: MYR 235,200 - 336,000 annually

Key Requirements

  • •8+ years of professional experience in physical design, preferably for high-performance designs.
  • •Closed high-performance IPs (e.g., CPU/GPU/DPU/memory controller) to signoff.
  • •Strong experience with logic synthesis, place and route, timing analysis, and physical/electrical design checks.
  • •Versatility with scripts to automate design flow (Perl/Tcl/Python).
  • •Experience with advanced sub 7nm nodes and strong physical design/timing background.
Experience:8+ yearsSemiconductorsGPUSoCHigh-performance design
Education:Bachelor's in Electronics/Electrical Engineering, Computer Engineering
Skills:Analytical skillsCommunicationProblem-solvingMulti-taskingAttention to detail
Tech Stack:RTLGDSIIFloor-planningPlace and routeTiming closureSignoffDRCLVSEM/IRSynthesisSynopsys Fusion CompilerCadencePrimeTimeStarRCCalibreApache RedhawkPerlTclPython

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
WebsiteLinkedIn