Principal Design Engineer

Cadence Design Systems
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 8+ yearsEducation: bachelorsSkills: ["Interpersonal","Communication"]

Design verification specialist focusing on interconnect IP and NoC-based subsystems, crafting and executing verification plans for highly complex, configurable designs. Collaborates with DV/Arch/Design/FW teams to define coverage scope, drives coverage collection and closure, and champions fully automated verification flows using SystemVerilog/UVM and related scripting. Strong emphasis on technical and interpersonal communication to solve advanced verification challenges.

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Cadence Design Systems
Cadence Design Systems
7 months ago

Principal Design Engineer

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 7 hours agoStatus: Live
Reposted: similar role first listed 9 months ago

Job Summary

Design verification specialist focusing on interconnect IP and NoC-based subsystems, crafting and executing verification plans for highly complex, configurable designs. Collaborates with DV/Arch/Design/FW teams to define coverage scope, drives coverage collection and closure, and champions fully automated verification flows using SystemVerilog/UVM and related scripting. Strong emphasis on technical and interpersonal communication to solve advanced verification challenges.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Design Verification for interconnect IP.
  • •Crafting verification plans and executing on those plans to verify highly complex and configurable designs.
  • •Responsible for coverage collection and closure.
  • •Work closely with cross functional teams (DV/Arch/Design/FW) to identify coverage scope.
  • •Experience with development of fully automated flows.

Key Requirements

  • •8+ years of design verification experience.
  • •BS (or higher) in EE/Computer Engineering.
  • •Thorough understanding of System Verilog, UVM, and other programming languages to build flexible and reusable complex testbenches.
  • •Excellent knowledge of Interconnects, NoCs and design verification fundamentals.
  • •Experience with development of fully automated flows.
Experience:8+ yearsInterconnectNoCsDesign verificationSemiconductors
Education:Bachelor's in Electrical Engineering / Computer Engineering
Skills:InterpersonalCommunication
Tech Stack:SystemVerilogUVMPerlUnix shellFormal VerificationGate Level Simulation

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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Glassdoor: 3.9
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