DFx Verification

AMD
Bengaluru
Workplace: OnsiteFull timeINR 3,338,160 - 4,768,800 annuallyFunction: QA, Test & Release EngineeringExperience: 8-10 yearsSkills: ["Communication","Analytical thinking","Problem-solving","Collaboration","Learning mindset"]

Own DFx verification across blocks, IP, subsystems, and SoC levels to drive first-pass silicon success. Build and maintain SystemVerilog/UVM verification environments (testbenches, stimulus, checkers, coverage, scoreboards), including scan/ATPG, LBIST/MBIST, JTAG/1149.x, and boundary scan flows. Define and close verification plans with coverage-driven metrics, run gate-level simulations with scan-inserted netlists, and collaborate with DFT/DFx architects and RTL designers to improve design-for-test and bring-up outcomes, regression, and automation.

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FursaFursa
AMD
AMD
2 days ago

DFx Verification

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Source: Company careers pageValidated by: Fursa AI
Last checked: 5 hours agoStatus: Live

Job Summary

Own DFx verification across blocks, IP, subsystems, and SoC levels to drive first-pass silicon success. Build and maintain SystemVerilog/UVM verification environments (testbenches, stimulus, checkers, coverage, scoreboards), including scan/ATPG, LBIST/MBIST, JTAG/1149.x, and boundary scan flows. Define and close verification plans with coverage-driven metrics, run gate-level simulations with scan-inserted netlists, and collaborate with DFT/DFx architects and RTL designers to improve design-for-test and bring-up outcomes, regression, and automation.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: QA, Test & Release Engineering
Seniority: Mid level

Key Responsibilities

  • •Own DFx verification for block/IP, subsystem, and SoC levels, including scan/ATPG, LBIST/MBIST, JTAG/1149.x, boundary scan, repair/debug, and test compression.
  • •Develop and maintain SystemVerilog/UVM testbenches and tests for DFx, including coverage-driven verification (stimulus, checkers, coverage, scoreboards).
  • •Define and execute DFx verification plans from specs/requirements and track/close using coverage-driven metrics.
  • •Build BFMs, agents, and monitors to verify interactions between DFx logic and key functional blocks (clocks/resets/power/fabric/memories) and create directed + constrained-random tests for scan insertion and repair/debug flows.
  • •Run gate-level simulations with scan-inserted netlists using SDF, partner with DFT/DFx architects and RTL designers on corner cases, and support post-silicon correlation, bring-up, pattern debug, and yield/quality improvements.

Pay and Benefits

Salary: INR 3,338,160 - 4,768,800 annually

Key Requirements

  • •8-10 years of experience with a B.Tech or M.Tech degree.
  • •Strong digital design verification experience using SystemVerilog and UVM (or similar verification methodologies).
  • •Hands-on DFx/DFT concepts and flows such as scan, ATPG patterns, and test compression.
  • •Experience with logic BIST (LBIST) and memory BIST (MBIST), including JTAG/IEEE 1149.x and boundary scan/test access mechanisms.
  • •Proficiency with scripting (Python, Perl, Tcl, or Shell) for automation/regressions and data analysis; experience with gate-level simulations is a plus.
Experience:8-10 yearsSemiconductorSoCDigital designSilicon verificationDFT/DFxHardware emulation
Education:
Skills:CommunicationAnalytical thinkingProblem-solvingCollaborationLearning mindset
Languages:English
Tech Stack:SystemVerilogUVMCC++DPIPythonPerlTclShellScanATPGTest compressionLBISTMBISTJTAGIEEE 1149.xBoundary scanSystemVerilog DPISDFUPF

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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