Research Engineer, Chip Design RL (Reinforcement Learning)

Anthropic
San Francisco, New York
Workplace: HybridFull timeUSD 500,000 - 850,000 annuallyFunction: Education & TrainingEducation: bachelorsSkills: ["Collaboration","Communication"]

Build reinforcement learning environments and evaluations that help models generate and optimize RTL for chip design, including formal verification and physical design optimization. Work on cross-cutting RL factors like EDA-tool latency optimization and proxy rewards, run experiments to shape the roadmap, and deliver results into research and production training. Collaborate closely with researchers and engineers across Anthropic at the intersection of ML and hardware.

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FursaFursa
Anthropic
Anthropic
2 months ago

Research Engineer, Chip Design RL (Reinforcement Learning)

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 5 hours agoStatus: Live

Job Summary

Build reinforcement learning environments and evaluations that help models generate and optimize RTL for chip design, including formal verification and physical design optimization. Work on cross-cutting RL factors like EDA-tool latency optimization and proxy rewards, run experiments to shape the roadmap, and deliver results into research and production training. Collaborate closely with researchers and engineers across Anthropic at the intersection of ML and hardware.
Location: San Francisco, New York
Workplace: Hybrid
Employment Type: Full time
Job Function: Education & Training

Key Responsibilities

  • •Invent, design, and implement RL environments and evaluations for agentic RTL generation, including design (formal) verification and physical design optimization.
  • •Work on cross-cutting RL considerations such as EDA-tool latency optimization and proxy rewards.
  • •Conduct experiments and help shape the roadmap.
  • •Deliver work into research and production training runs.
  • •Collaborate with researchers and engineers across and outside Anthropic.

Pay and Benefits

Salary: USD 500,000 - 850,000 annually
Perks:Parental LeavePaid LeaveEquity

Key Requirements

  • •Expertise in ASIC or FPGA design, including RTL, design verification (UVM, formal methods, coverage-driven), and physical design (synthesis, place-and-route, timing closure).
  • •Knowledge of PPA optimization, DFT, and ECOs, and the ability to implement end-to-end chip flows.
  • •Fluency with industry EDA tools and processes.
  • •Experience going from specification to silicon, including having taped out chips.
  • •Ability to balance research exploration with engineering implementation.
Experience:Reinforcement learningASICFPGAHardware design
Education:Bachelor's
Skills:CollaborationCommunication
Languages:English
Tech Stack:ASICFPGARTLUVMFormal methodsCoverage-driven verificationPhysical designSynthesisPlace-and-routeTiming closurePPA optimizationDFTECOsEDA toolsReinforcement learningAgentic RTL generationFormal verificationProxy rewardsHigh-level synthesisArchitecture simulators

Eligibility

Work Authorization:Sponsorship available.

Company Brief

Anthropic
Develops large-scale AI systems and safety research to create reliable, steerable, and interpretable AI assistants and models for commercial and research applications.
Industry: AI & Machine Learning
Company Size: Enterprise (1,001+ employees)
Growth: Scaleup
Valuation: Unicorn (USD 1B+)
Funding: Series C
Headquarters: San Francisco, United States
Founded: 2021
WebsiteLinkedIn