Principal Engineer

Lead ASIC design activities for 5nm/3nm CMOS cell-based ASICs, spanning RTL analysis, synthesis, timing verification, physical design, and post-prototype support. Collaborate with internal/external customers to deliver state-of-the-art IC solutions, including full-chip synthesis/STA, floorplanning, and DRC/LVS. Strong problem-solving and communication skills required; familiarity with advanced design flows a plus.