Sr. Principal Design Engineer

Cadence Design Systems
Noida
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Education: mastersSkills: ["Strong analytical skills","Problem-solving","Attention to detail","Cross-functional collaboration"]

Develop SRAM/Register File circuits for low-power, low-voltage and high-performance memory designs. Build and optimize SRAM macros, sense amplifiers, and self-timed circuits, then run SPICE simulations to evaluate timing, power, and Static Noise Margin across process corners. Supervise layout/physical design for FinFET rules and support post-silicon validation, debugging hardware failures. Use Cadence Virtuoso and automation with Python or Perl.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
Cadence Design Systems
Cadence Design Systems
4 days ago

Sr. Principal Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 4 hours agoStatus: Live
Reposted: similar role first listed 7 months ago

Job Summary

Develop SRAM/Register File circuits for low-power, low-voltage and high-performance memory designs. Build and optimize SRAM macros, sense amplifiers, and self-timed circuits, then run SPICE simulations to evaluate timing, power, and Static Noise Margin across process corners. Supervise layout/physical design for FinFET rules and support post-silicon validation, debugging hardware failures. Use Cadence Virtuoso and automation with Python or Perl.
Location: Noida
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Sr. Manager level

Key Responsibilities

  • •Build full-custom or compiler-based SRAM macros, sense amplifiers, and self-timed circuits.
  • •Run SPICE simulations to analyze timing, power, and Static Noise Margin (SNM) across process corners.
  • •Direct physical design and layout teams to address process variability and FinFET manufacturing rules.
  • •Support post-silicon testing and troubleshoot hardware failures.
  • •Collaborate with circuit designers, architecture teams, and CAD engineers to deliver memory development work.

Key Requirements

  • •B.Tech/M.Tech in Electrical Engineering, VLSI, or Microelectronics.
  • •6–18 years of experience (range depends on entry/mid vs senior lead/architect level).
  • •Deep understanding of CMOS device physics, transistor sizing, and memory cell stability.
  • •Proficiency in EDA tools such as Cadence Virtuoso and/or SPICE simulators.
  • •Ability to use Python or Perl for workflow automation and data analysis.
Experience:SemiconductorVLSIMemory designSRAM
Education:Master's in Electrical Engineering, VLSI, or Microelectronics
Skills:Strong analytical skillsProblem-solvingAttention to detailCross-functional collaboration
Tech Stack:SRAMRegister FileSPICECadence VirtuosoEDAPythonPerlCMOSFinFET

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
Glassdoor
Glassdoor: 3.9
WebsiteLinkedInGlassdoor