Senior RTL Engineer, Interconnect Design
OpenAI
San Francisco
Workplace: HybridFull timeUSD 225,000 - 445,000 annuallyFunction: Design (Product/UX/UI/Visual)Skills: ["Verilog","SystemVerilog","RTL","Microarchitecture","NoC","PCIe","AXI","RAM","Memory subsystem","Timing analysis","Verification","Design-for-test"]Lead ownership of RTL interconnect designs for OpenAI's AI accelerator platform, driving microarchitecture, RTL implementation, and verification of high-bandwidth on-chip fabrics and off-chip interfaces. Collaborate across architecture, design, verification, physical design, and external partners to deliver production-quality silicon for large-scale AI training and inference. This senior, hands-on role includes mentoring junior engineers and shaping performance targets; based in San Francisco with a hybrid schedule and relocation support.
