RTL Design Engineer – Interconnect & Network Datapath

OpenAI
San Francisco
Workplace: HybridFull timeUSD 225,000 - 445,000 annuallyFunction: Design (Product/UX/UI/Visual)Skills: ["Verilog","SystemVerilog","RTL","Microarchitecture","NoC","PCIe","AXI","RAM","Memory subsystem","Timing analysis","Verification","Design-for-test"]

Lead ownership of RTL interconnect designs for OpenAI's AI accelerator platform, driving microarchitecture, RTL implementation, and verification of high-bandwidth on-chip fabrics and off-chip interfaces. Collaborate across architecture, design, verification, physical design, and external partners to deliver production-quality silicon for large-scale AI training and inference. This senior, hands-on role includes mentoring junior engineers and shaping performance targets; based in San Francisco with a hybrid schedule and relocation support.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
OpenAI
OpenAI
2 months ago

RTL Design Engineer – Interconnect & Network Datapath

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 47 minutes agoStatus: Live

Job Summary

Lead ownership of RTL interconnect designs for OpenAI's AI accelerator platform, driving microarchitecture, RTL implementation, and verification of high-bandwidth on-chip fabrics and off-chip interfaces. Collaborate across architecture, design, verification, physical design, and external partners to deliver production-quality silicon for large-scale AI training and inference. This senior, hands-on role includes mentoring junior engineers and shaping performance targets; based in San Francisco with a hybrid schedule and relocation support.
Location: San Francisco
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Sr. Manager level

Key Responsibilities

  • •Own microarchitecture, RTL design, and delivery of major interconnect components (NoC fabrics, switches, routers, bridges, protocol adapters) and off-chip interfaces.
  • •Drive third-party engagements to develop networking protocols and silicon IP while ensuring design integrity.
  • •Perform direct microarchitecture and RTL coding work and collaborate on architecture and execution plans for large-scale silicon.
  • •Collaborate with architecture, verification, and physical design teams to optimize interconnects for target frequency, power, and area.
  • •Provide technical leadership through design reviews, mentoring, and reusable RTL/integration methodologies.

Pay and Benefits

Salary: USD 225,000 - 445,000 annually
Equity and Bonus:Equity
Perks:EquityRelocation

Key Requirements

  • •Proven experience in RTL design and microarchitecture for complex interconnects (NoC, coherent fabric, memory subsystem) and chip-level integration
  • •Deep expertise in Verilog/SystemVerilog with production-quality RTL
  • •Experience with on-chip or chip-to-chip protocols (AXI, APB, PCIe, Ethernet) and off-chip interfaces
  • •Strong track record of owning RTL blocks or SoC subsystems from microarchitecture to tape-out and silicon bring-up
  • •Excellent communication and leadership skills with ability to mentor engineers and drive cross-team alignment
Experience:SemiconductorHardwareSoCInterconnectNoC
Skills:VerilogSystemVerilogRTLMicroarchitectureNoCPCIeAXIRAMMemory subsystemTiming analysisVerificationDesign-for-test
Languages:English
Tech Stack:VerilogSystemVerilogRTLNoCAXIAPBCXLPCIeEthernetRDMARoCE

Company Brief

OpenAI
Develops and deploys advanced generative AI models (including ChatGPT and DALL·E) and AI infrastructure, providing APIs and consumer products to accelerate safe AGI for broad benefit.
Industry: AI & Machine Learning
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Scaleup
Valuation: Hectocorn (USD 100B+)
Funding: Series E+
Headquarters: San Francisco, United States
Founded: 2015
Glassdoor
Glassdoor: 4.4
WebsiteLinkedInGlassdoor