1 day ago

Principal DFT Engineer (Silicon Engineering)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 15 hours agoStatus: Live

Job Summary

Develop and optimize DFT architectures for next-generation ASICs used in Starlink space and ground infrastructure. Lead scan insertion and ATPG methodologies, generate fault-model patterns, and support post-silicon validation. Evaluate scan readiness via RTL and DRC checks, integrate DFT fabrics and IP across subsystems, and run/debug gate-level simulations. Automate test flows and analyze data using scripting languages.

Location: Irvine, Austin, Palo Alto

Workplace: Onsite

Employment Type: Full time

Job Function: Communications, PR & Community

Key Responsibilities

•Lead implementation and optimization of DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST using Siemens Tessent tools
•Own ATPG tools and methodologies, including generating patterns for stuck-at, transition, and path delay fault models, with focus on compression, diagnosis, and hierarchical test flows; provide post-silicon testing support
•Evaluate design readiness for scan insertion using RTL and physical design Scan DRC tools
•Integrate and verify DFT fabrics and IP within subsystems
•Run and debug non-timing and SDF-annotated gate-level simulations, and develop test scripts to automate processes and analyze data

Pay and Benefits

Salary: USD 210,000 - 340,000 annually

Equity and Bonus:Equity

Perks:Health InsuranceVisionDental401kDisability InsuranceLife InsurancePaid ParentalPaid LeavePaid Holidays

Key Requirements

•Bachelor’s degree in electrical engineering, computer engineering, or computer science
•10+ years of experience working with ASICs
•10+ years of experience in scan insertion and DFT setup, integration, and validation
•Strong RTL experience to understand, trace, and debug RTL connectivity issues as they relate to DFT
•Experience using UPF (Unified Power Format), formal verification, and DRC rule checking

Experience:10+ years

Education:Bachelor's

Skills:LeadershipProblem-solvingProactiveIntellectually curious

Languages:En

Tech Stack:ASICsDFTScan insertionSiemens TessentATP GStuck-atTransitionPath delayPattern compressionHierarchical testDRCRTLSDFGate-level simulationsPerlPythonTclC++UPFFormal verification

Eligibility

Nationality:US National

Company Brief

SpaceX

Designs, manufactures, and launches advanced rockets and spacecraft for commercial and government customers, aiming to reduce space transportation costs and enable human life on Mars through reusable launch vehicles and integrated space systems.

Industry: Aerospace Manufacturing

Company Size: Enterprise (1,001+ employees)

Growth: Established Company

Valuation: Hectocorn (USD 100B+)

Funding: Series E+

Headquarters: Hawthorne, United States

Founded: 2002

Glassdoor: 4.2

Website LinkedIn

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SpaceX

1 day ago

Principal DFT Engineer (Silicon Engineering)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 15 hours agoStatus: Live

Job Summary

Location: Irvine, Austin, Palo Alto

Workplace: Onsite

Employment Type: Full time

Job Function: Communications, PR & Community

Key Responsibilities

•Lead implementation and optimization of DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST using Siemens Tessent tools
•Own ATPG tools and methodologies, including generating patterns for stuck-at, transition, and path delay fault models, with focus on compression, diagnosis, and hierarchical test flows; provide post-silicon testing support
•Evaluate design readiness for scan insertion using RTL and physical design Scan DRC tools
•Integrate and verify DFT fabrics and IP within subsystems
•Run and debug non-timing and SDF-annotated gate-level simulations, and develop test scripts to automate processes and analyze data

Pay and Benefits

Salary: USD 210,000 - 340,000 annually

Equity and Bonus:Equity

Perks:Health InsuranceVisionDental401kDisability InsuranceLife InsurancePaid ParentalPaid LeavePaid Holidays

Key Requirements

•Bachelor’s degree in electrical engineering, computer engineering, or computer science
•10+ years of experience working with ASICs
•10+ years of experience in scan insertion and DFT setup, integration, and validation
•Strong RTL experience to understand, trace, and debug RTL connectivity issues as they relate to DFT
•Experience using UPF (Unified Power Format), formal verification, and DRC rule checking

Experience:10+ years

Education:Bachelor's

Skills:LeadershipProblem-solvingProactiveIntellectually curious

Languages:En

Tech Stack:ASICsDFTScan insertionSiemens TessentATP GStuck-atTransitionPath delayPattern compressionHierarchical testDRCRTLSDFGate-level simulationsPerlPythonTclC++UPFFormal verification

Eligibility

Nationality:US National

Company Brief

SpaceX

Industry: Aerospace Manufacturing

Company Size: Enterprise (1,001+ employees)

Growth: Established Company

Valuation: Hectocorn (USD 100B+)

Funding: Series E+

Headquarters: Hawthorne, United States

Founded: 2002

Glassdoor: 4.2

Website LinkedIn