NVIDIA

4 weeks ago

Principal DRAM Architect – GPU Memory Solutions

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 1 hour agoStatus: Live

Job Summary

Lead the architecture and roadmap of next-generation DRAM for GPU memory solutions, shaping high-speed interfaces, memory packaging, and reliability strategies. Collaborate across DRAM vendors and JEDEC to influence standards, optimize co-packaged DRAM–GPU solutions, and balance bandwidth, latency, power, and cost. Mentor engineers and drive NVIDIA’s long-term memory architecture vision across AI, graphics, data center, and automotive platforms.

Location: Santa Clara

Workplace: Hybrid

Employment Type: Full time

Job Function: Solutions Engineering & Sales Engineering

Seniority: Sr. Manager level

Key Responsibilities

•Architect next-generation DRAM solutions and NVIDIA-specific implementations — including bank and stack structures, refresh mechanisms, retention schemes, ECC/CRC, power management, and reliability optimization.
•Lead innovation in high-speed memory interfaces, with deep expertise in HBM PHYs (wide I/O, TSV signaling, SI/PI, timing margins) and an understanding of GDDR/LPDDR PHY architectures.
•Collaborate across domains on advanced packaging technologies (TSVs, interposers, CoWoS, hybrid bonding, FOWLP) to optimize DRAM–GPU co-packaging for bandwidth, power, thermal performance, and yield.
•Evaluate emerging DRAM process nodes (sub-1x nm, EUV, new capacitor/dielectric materials) and their impact on density, power, retention, and cost.
•Influence industry direction by working with DRAM vendors and actively contributing to JEDEC committees, driving next-generation memory standards and NVIDIA-specific roadmap alignment.

Pay and Benefits

Salary: USD 272,000 - 431,250 annually

Equity and Bonus:Equity

Perks:Equity

Key Requirements

•MS or PhD in Electrical Engineering, Computer Engineering, Physics (or equivalent experience).
•15+ years of experience in DRAM or memory system architecture, with at least 5+ years focused on HBM (HBM2/2e/3/3e or next-gen).
•Expertise in HBM architecture: TSV design, die stacking, interposer/CoWoS integration, refresh schemes, ECC/CRC, pseudo-channels, and thermal/power management.
•Proven participation in JEDEC or equivalent standards organizations, contributing to DRAM or HBM specifications.
•Demonstrated ability to influence DRAM vendor roadmaps, negotiate trade-offs, and enable early silicon validation.

Experience:15+ yearsMemory architectureHBMDRAMJEDECHigh-bandwidth memory

Education:Master's

Skills:HBMGDDRLPDDRDSOITSVInterposerCoWoSECCCRCPHY designTimingSI/PIJitter budgetingThermal managementPackagingMemory interfaces

Tech Stack:HBMGDDRLPDDRTSVCoWoSInterposerFOWLPEUVECCCRC

Company Brief

NVIDIA

Designs and manufactures GPUs, AI accelerators, and system-on-chip products for gaming, data centers, professional visualization, and automotive markets, enabling advanced graphics, AI, and high-performance computing solutions worldwide.

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1993

Glassdoor: 4.3

Website LinkedIn Glassdoor

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NVIDIA

4 weeks ago

Principal DRAM Architect – GPU Memory Solutions

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI

Last checked: 1 hour agoStatus: Live

Job Summary

Location: Santa Clara

Workplace: Hybrid

Employment Type: Full time

Job Function: Solutions Engineering & Sales Engineering

Seniority: Sr. Manager level

Key Responsibilities

•Architect next-generation DRAM solutions and NVIDIA-specific implementations — including bank and stack structures, refresh mechanisms, retention schemes, ECC/CRC, power management, and reliability optimization.
•Lead innovation in high-speed memory interfaces, with deep expertise in HBM PHYs (wide I/O, TSV signaling, SI/PI, timing margins) and an understanding of GDDR/LPDDR PHY architectures.
•Collaborate across domains on advanced packaging technologies (TSVs, interposers, CoWoS, hybrid bonding, FOWLP) to optimize DRAM–GPU co-packaging for bandwidth, power, thermal performance, and yield.
•Evaluate emerging DRAM process nodes (sub-1x nm, EUV, new capacitor/dielectric materials) and their impact on density, power, retention, and cost.
•Influence industry direction by working with DRAM vendors and actively contributing to JEDEC committees, driving next-generation memory standards and NVIDIA-specific roadmap alignment.

Pay and Benefits

Salary: USD 272,000 - 431,250 annually

Equity and Bonus:Equity

Perks:Equity

Key Requirements

•MS or PhD in Electrical Engineering, Computer Engineering, Physics (or equivalent experience).
•15+ years of experience in DRAM or memory system architecture, with at least 5+ years focused on HBM (HBM2/2e/3/3e or next-gen).
•Expertise in HBM architecture: TSV design, die stacking, interposer/CoWoS integration, refresh schemes, ECC/CRC, pseudo-channels, and thermal/power management.
•Proven participation in JEDEC or equivalent standards organizations, contributing to DRAM or HBM specifications.
•Demonstrated ability to influence DRAM vendor roadmaps, negotiate trade-offs, and enable early silicon validation.

Experience:15+ yearsMemory architectureHBMDRAMJEDECHigh-bandwidth memory

Education:Master's

Skills:HBMGDDRLPDDRDSOITSVInterposerCoWoSECCCRCPHY designTimingSI/PIJitter budgetingThermal managementPackagingMemory interfaces

Tech Stack:HBMGDDRLPDDRTSVCoWoSInterposerFOWLPEUVECCCRC

Company Brief

NVIDIA

Industry: Electronics Manufacturing

Company Size: Enterprise (1,001+ employees)

Revenue: USD 1B+

Growth: Public Company

Valuation: Public Company (Market Cap in USD)

Funding: IPO / Publicly Listed

Headquarters: Santa Clara, United States

Founded: 1993

Glassdoor: 4.3

Website LinkedIn Glassdoor