Sr Principal Design Engineer

Cadence Design Systems
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 12-14 yearsEducation: mastersSkills: []

Lead and deliver advanced VLSI design verification projects in a hands-on role, applying Verilog and HVL with UVM/OVM/eRM methodologies to develop test-benches, RTL/GLS simulations, and formal verification. Manage project delivery, automate verification flows with Perl/Tcl, and ensure robust assertions, coverage, and debugging across complex silicon designs.

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Cadence Design Systems
Cadence Design Systems
6 months ago

Sr Principal Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 7 hours agoStatus: Live
Reposted: similar role first listed 9 months ago

Job Summary

Lead and deliver advanced VLSI design verification projects in a hands-on role, applying Verilog and HVL with UVM/OVM/eRM methodologies to develop test-benches, RTL/GLS simulations, and formal verification. Manage project delivery, automate verification flows with Perl/Tcl, and ensure robust assertions, coverage, and debugging across complex silicon designs.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Manager level

Key Responsibilities

  • •Lead and deliver VLSI verification projects, managing schedule and delivery independently.
  • •Develop and maintain test-benches and RTL/GLS simulation environments with debugging as needed.
  • •Implement Verilog/HVL-based verification flows using UVM/OVM/eRM methodologies.
  • •Develop and close assertions, perform constraint randomization, and achieve functional and code coverage; apply formal verification techniques.
  • •Automate verification tasks using Perl/Tcl scripting to improve efficiency and reliability.

Key Requirements

  • •12-14 yrs of work experiences in VLSI domain with Master’s/bachelor’s degree in engineering
  • •Strong expertise in Verilog, HVL(SV, Specman e) with UVM/OVM/eRM methodology
  • •Expertise in assertions development/closure, constraint randomization, functional and code coverages, formal verification
  • •Expertise in test-bench development
  • •Strong RTL and GLS (w/ or w/o SDF) sim debug skills
Experience:12-14 yearsVLSISemiconductorHardware design
Education:Master's in Engineering
Tech Stack:VerilogHVLSVSpecman eUVMOVMERMAssertionsConstraint randomizationFunctional coverageCode coverageFormal verificationTest benchRTLGLSSDFPerlTcl

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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