Design Verification Engineer

Broadcom
San Jose
Workplace: OnsiteFull timeUSD 143,800 - 230,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 12+ yearsEducation: bachelorsSkills: ["SystemVerilog","UVM","C/C++","Perl","Scripting"]

Join Broadcom\'s ASIC Product Division to perform system- and block-level verification for SoC and IP. You will develop verification environments with SystemVerilog/UVM, create verification components and test cases, implement coverage and assertions, and analyze simulation results to ensure high-quality designs.

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FursaFursa
Broadcom
Broadcom
3 months ago

Design Verification Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 33 days agoStatus: Live
Reposted: similar role first listed 7 months ago

Job Summary

Join Broadcom\'s ASIC Product Division to perform system- and block-level verification for SoC and IP. You will develop verification environments with SystemVerilog/UVM, create verification components and test cases, implement coverage and assertions, and analyze simulation results to ensure high-quality designs.
Location: San Jose
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Develop verification environments using modern verification techniques (SystemVerilog and UVM) to verify designs at system and sub-block levels.
  • •Design verification components such as UVM agents and behavioral models to support robust testing.
  • •Implement coverage and assertions using SystemVerilog and develop random and directed test cases against specifications.
  • •Analyze and debug simulation failures and coverage results to identify root causes and improve test quality.
  • •Collaborate with verification and design teams to address complex verification trade-offs and ensure timely delivery.

Pay and Benefits

Salary: USD 143,800 - 230,000 annually
Equity and Bonus:Equity
Perks:Health InsuranceDentalVision401kEsppEapPaid HolidaysPaid LeaveParental Leave

Key Requirements

  • •Bachelor\'s Degree in Electrical and Electronic Engineering, Computer Science, or equivalent
  • •12+ years of relevant industry work experience
  • •Fluent knowledge of RTL verification methodologies including SystemVerilog
  • •Strong working knowledge of object oriented verification languages (OVM, UVM, etc.), C/C++, Perl, and scripting
  • •Must have legal authorization to work in the US
Experience:12+ yearsSemiconductorHardwareASICSoC
Education:Bachelor's
Skills:SystemVerilogUVMC/C++PerlScripting
Languages:English
Tech Stack:SystemVerilogUVMCC++PerlScripting

Eligibility

Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

Broadcom
Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Irvine, United States
Founded: 1991
WebsiteLinkedIn