Design Verification Engineer
Broadcom
San Jose
Workplace: OnsiteFull timeUSD 143,800 - 230,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 12+ yearsEducation: bachelorsSkills: ["SystemVerilog","UVM","C/C++","Perl","Scripting"]Join Broadcom\'s ASIC Product Division to perform system- and block-level verification for SoC and IP. You will develop verification environments with SystemVerilog/UVM, create verification components and test cases, implement coverage and assertions, and analyze simulation results to ensure high-quality designs.

