Mixed- Signal Systems and Verification Engineer

Cadence Design Systems
Bengaluru
Full timeFunction: QA, Test & Release EngineeringSkills: ["Teamwork","Communication"]

Join a hands-on engineering team focused on mixed-signal/analog verification. Develop accurate, simulation-efficient analog behavioral models in SystemVerilog for analog/RF blocks, integrate them with RTL, and validate model behavior against design specifications using test benches, test scenarios, and assertions. Document modeling and verification results for formal review, with opportunities to use low-power architecture knowledge, analog assertion-based verification, and scripting (Perl/Python).

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Cadence Design Systems
Cadence Design Systems
12 hours ago

Mixed- Signal Systems and Verification Engineer

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Last checked: 12 hours agoStatus: Live

Job Summary

Join a hands-on engineering team focused on mixed-signal/analog verification. Develop accurate, simulation-efficient analog behavioral models in SystemVerilog for analog/RF blocks, integrate them with RTL, and validate model behavior against design specifications using test benches, test scenarios, and assertions. Document modeling and verification results for formal review, with opportunities to use low-power architecture knowledge, analog assertion-based verification, and scripting (Perl/Python).
Location: Bengaluru
Employment Type: Full time
Job Function: QA, Test & Release Engineering
Seniority: Graduate level

Key Responsibilities

  • •Develop accurate, simulation-efficient analog behavioral models for analog/RF blocks in SystemVerilog.
  • •Verify that behavior models accurately represent analog schematics and integrate models with RTL.
  • •Validate analog functionality against design specifications using coding test benches, test scenarios, and assertions.
  • •Use analog behavioral models to support verification of analog functionalities (including documentation for formal review).
  • •Document modeling and verification results for formal review.

Key Requirements

  • •New graduates strongly encouraged to apply.
  • •Experience developing and verifying real-numbered behavioral models in SystemVerilog.
  • •Understanding SystemVerilog and concepts such as RNM and UDN/UDT/UDR, wreal, and Verilog-AMS.
  • •Basic understanding of AMS blocks (e.g., filters, ADC, DAC, VCO, A/DPLL, SerDes, LNA, mixer).
  • •Experience with Cadence Virtuoso Schematic Composer and ADE, plus analog assertion-based verification (TB development is a plus).
Skills:TeamworkCommunication
Tech Stack:SystemVerilogRNMUDNUDTUDRWrealVerilog-AMSPerlPythonCadence Virtuoso Schematic ComposerADE

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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