Principal Design Engineer

Cadence Design Systems
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 7+ yearsEducation: bachelorsSkills: ["Communication"]

Join a dynamic team developing high-performance SerDes physical IP. You will contribute to digital architecture, RTL and low-power design, perform synthesis and timing analysis, and drive tool flows for IP quality control. Collaborate with design architects, verification, and analog/digital teams across worldwide sites to refine features, constraints, and architecture from micro-architecture to RTL, delivering high-quality results on schedule.

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FursaFursa
Cadence Design Systems
Cadence Design Systems
6 months ago

Principal Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 7 hours agoStatus: Live
Reposted: similar role first listed 9 months ago

Job Summary

Join a dynamic team developing high-performance SerDes physical IP. You will contribute to digital architecture, RTL and low-power design, perform synthesis and timing analysis, and drive tool flows for IP quality control. Collaborate with design architects, verification, and analog/digital teams across worldwide sites to refine features, constraints, and architecture from micro-architecture to RTL, delivering high-quality results on schedule.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Sr. Manager level

Key Responsibilities

  • •Contribute to digital architecture, RTL, and low-power design for SerDes IP portfolio.
  • •Drive architecture from micro-architecture to RTL implementation and refine features/requirements throughout the design process.
  • •Collaborate with verification, project management, and analog/digital design teams across geographies to ensure IP quality and timely delivery.
  • •Understand synthesis, constraints, power management and DFT, and assist with tool flows for IP quality control.
  • •Work with the IPG development team on diverse tasks including embedded uC subsystems and cross-functional design reviews.

Key Requirements

  • •7+ years of experience in Digital Design and Architecture.
  • •Strong written and verbal cross-functional communication skills.
Experience:7+ yearsSemiconductorHardwareASIC
Education:Bachelor's
Skills:Communication
Tech Stack:SystemVerilogPythonC/C++PerforceGitSVNScriptingRTLSynthesisSDC

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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Glassdoor: 3.9
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