Sr. RTL Design Engineer (Silicon Engineering)
SpaceX
Sunnyvale
Workplace: OnsiteFull timeUSD 170,000 - 235,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: bachelorsSkills: ["Verilog","SystemVerilog","RTL","Python","HDL","EDA tools","ASIC","SoC","AXI","AHB","High speed design","Low power design"]Hardware-focused RTL design engineer to develop next-generation ASICs for SpaceX Starlink, collaborating with cross-disciplinary teams to implement and verify RTL in Verilog/SystemVerilog, support timing closure, and assist silicon bring-up for space/ground infrastructure.
