Sr. RTL Design Engineer (Silicon Engineering)

SpaceX
Sunnyvale
Workplace: OnsiteFull timeUSD 170,000 - 235,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: bachelorsSkills: ["Verilog","SystemVerilog","RTL","Python","HDL","EDA tools","ASIC","SoC","AXI","AHB","High speed design","Low power design"]

Hardware-focused RTL design engineer to develop next-generation ASICs for SpaceX Starlink, collaborating with cross-disciplinary teams to implement and verify RTL in Verilog/SystemVerilog, support timing closure, and assist silicon bring-up for space/ground infrastructure.

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FursaFursa
SpaceX
SpaceX
3 months ago

Sr. RTL Design Engineer (Silicon Engineering)

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Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 15 hours agoStatus: Live
Reposted: similar role first listed 6 months ago

Job Summary

Hardware-focused RTL design engineer to develop next-generation ASICs for SpaceX Starlink, collaborating with cross-disciplinary teams to implement and verify RTL in Verilog/SystemVerilog, support timing closure, and assist silicon bring-up for space/ground infrastructure.
Location: Sunnyvale
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Sr. Manager level

Key Responsibilities

  • •Evaluate architectural trade-offs based on features, performance requirements and system limitations.
  • •Define micro-architecture, implement the RTL in Verilog/SystemVerilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design.
  • •Work closely with verification team to ensure all aspects of the design are covered and verified.
  • •Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check).
  • •Participate in silicon bring-up and validation.

Pay and Benefits

Salary: USD 170,000 - 235,000 annually
Perks:Health InsuranceVisionDental401kLife InsurancePaid ParentalPaid LeaveDisability Insurance

Key Requirements

  • •Bachelor’s degree in electrical engineering, computer engineering, or computer science
  • •5+ years of experience in RTL implementation
  • •Ability to solve complex problems including clock domain crossings and power optimization
  • •ASIC/SoC system integration experience
  • •Experience with embedded CPU subsystems
Experience:5+ yearsSpaceAerospaceHardwareSemiconductor
Education:Bachelor's
Skills:VerilogSystemVerilogRTLPythonHDLEDA toolsASICSoCAXIAHBHigh speed designLow power design
Languages:English
Tech Stack:VerilogSystemVerilogRTLPythonEDA toolsHDLASICSoCAXIAHB

Company Brief

SpaceX
Designs, manufactures, and launches advanced rockets and spacecraft for commercial and government customers, aiming to reduce space transportation costs and enable human life on Mars through reusable launch vehicles and integrated space systems.
Industry: Aerospace Manufacturing
Company Size: Enterprise (1,001+ employees)
Growth: Established Company
Valuation: Hectocorn (USD 100B+)
Funding: Series E+
Headquarters: Hawthorne, United States
Founded: 2002
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