Senior Principal DFT Design Engineer

Cadence Design Systems
Anywhere
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Skills: ["Problem-solving","Collaboration","Self-driven","Methodical approach","Stakeholder management"]

Design for Test (DFT) role for SoC/ASIC: develop and execute scan chain insertion, compression scan insertion, MBIST/ LBIST flows, and ATPG to meet design test coverage goals. Drive systematic, quality-metrics-based ATPG pattern generation, debug and analyze failures to improve fault coverage, and verify testbenches by resolving simulation mis-compares. Collaborate across cross-functional stakeholders and deliver DFT tasks independently.

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Cadence Design Systems
Cadence Design Systems
1 month ago

Senior Principal DFT Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 7 hours agoStatus: Live
Reposted: similar role first listed 1 month ago

Job Summary

Design for Test (DFT) role for SoC/ASIC: develop and execute scan chain insertion, compression scan insertion, MBIST/ LBIST flows, and ATPG to meet design test coverage goals. Drive systematic, quality-metrics-based ATPG pattern generation, debug and analyze failures to improve fault coverage, and verify testbenches by resolving simulation mis-compares. Collaborate across cross-functional stakeholders and deliver DFT tasks independently.
Location: Anywhere
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Sr. Manager level

Key Responsibilities

  • •Perform DFT work for SoC/ASIC, including scan chain insertion and compression scan insertion.
  • •Apply MBIST/LBIST and execute quality-metrics-driven ATPG pattern generation to meet coverage goals.
  • •Debug and analyze failures to improve fault coverage and resolve simulation mis-compares.
  • •Verify ATPG testbenches and investigate root-cause issues across verification workflows.
  • •Coordinate with cross-functional stakeholders (architecture, design, internal and external customers) and complete DFT tasks independently.

Key Requirements

  • •10-20 years of professional experience in SoC/ASIC digital design with a focus on Design for Test (DFT).
  • •Deep knowledge of DFT insertion flows, including scan chain insertion and related synthesis/tool-based flows.
  • •Hands-on experience with compression scan insertion, LBIST, and other scan technologies.
  • •Expertise in MBIST and Automatic Test Pattern Generation (ATPG) to achieve design test coverage goals.
  • •Strong ability to debug and analyze failures and verify ATPG testbenches, including root-cause analysis for simulation mis-compares.
Experience:SoC/ASICDFTATPG
Skills:Problem-solvingCollaborationSelf-drivenMethodical approachStakeholder management
Tech Stack:DFTScan chain insertionCompression scanMBISTLBISTATPGSynthesisVerilogJTAG 1149.1JTAG 1149.6IEEE1500IEEE1687TestbenchesCadence tools

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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Glassdoor: 3.9
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