Senior Design Engineer, Coherent High Speed Interconnect
NVIDIA
Santa Clara
Workplace: HybridFull time168,000 - 310,500 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 8-8 yearsEducation: bachelorsSkills: ["Verilog","SystemVerilog","PCIe","CXL","AXI","CHI","DDR","LPDDR","SerDes","RTL design","Power optimization"]Senior Design Engineer for NVIDIA’s Coherent High Speed Interconnect team, focused on architecture and design of high-speed NVLINK-C2C interconnects for mobile SoCs and GPUs. Collaborates with architects, external partners, software engineers, and circuit designers to deliver a class-leading interconnect, enabling chiplet-based integration across GPUs, DPUs, and CPUs, with emphasis on RTL design and power optimization.
