Physical Design Engineering Graduate Intern

Intel
Santa Clara, Phoenix
Workplace: OnsiteInternshipUSD 89,900 - 121,600 annuallyFunction: Design (Product/UX/UI/Visual)Education: mastersSkills: ["Communication","Collaboration","Continuous learning","Problem-solving","Adaptability"]

Join Intel as a Physical Design Engineering Graduate Intern to support the physical implementation of advanced silicon designs. Work with a multidisciplinary team on synthesis, place-and-route, timing analysis, clocking, floorplanning, and clock tree synthesis. Help with verification and signoff to ensure manufacturability and performance compliance, apply power optimization strategies, and contribute to automation and design scalability using static timing analysis and low-power design techniques.

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Intel
Intel
4 days ago

Physical Design Engineering Graduate Intern

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Last checked: 5 hours agoStatus: Live

Job Summary

Join Intel as a Physical Design Engineering Graduate Intern to support the physical implementation of advanced silicon designs. Work with a multidisciplinary team on synthesis, place-and-route, timing analysis, clocking, floorplanning, and clock tree synthesis. Help with verification and signoff to ensure manufacturability and performance compliance, apply power optimization strategies, and contribute to automation and design scalability using static timing analysis and low-power design techniques.
Location: Santa Clara, Phoenix
Workplace: Onsite
Employment Type: Internship
Job Function: Design (Product/UX/UI/Visual)
Seniority: Intern level

Key Responsibilities

  • •Support physical design implementation processes including synthesis, place-and-route, timing analysis, clocking, and/or integration.
  • •Assist in verification and signoff activities to ensure manufacturability and performance compliance.
  • •Collaborate with cross-functional teams to enhance design scalability and automation efforts.
  • •Apply design optimization techniques to improve power, performance, and area efficiency.
  • •Perform floor planning and clock tree synthesis and contribute to static timing analysis to meet timing constraints.

Pay and Benefits

Salary: USD 89,900 - 121,600 annually
Perks:Health InsuranceRetirementPaid LeaveEquity

Key Requirements

  • •Currently pursuing a master’s degree in electrical engineering or computer engineering, or a related technical specialized field.
  • •3+ months of experience with physical design tools and flows, including design planning, floor planning, and static timing analysis.
  • •Knowledge of low-power design techniques and power reduction methodologies.
  • •Familiarity with clock tree synthesis and design optimization principles.
  • •Ability to analyze and solve complex technical problems.
Experience:Silicon design
Education:Master's
Skills:CommunicationCollaborationContinuous learningProblem-solvingAdaptability

Company Brief

Intel
Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1968
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