Full Chip Timing Lead

AMD
Hyderabad
Workplace: OnsiteFull timeINR 3,338,160 - 4,768,800 annuallyFunction: Administration & Executive AssistanceExperience: 8+ yearsEducation: bachelorsSkills: ["Communication","Collaboration","Self-driving","Organization","Automation affinity"]

Own full-chip timing closure for SoC designs, including high-frequency CPU and HBM/DDR/SerDes interfaces. Drive clock build guidance, SDC validation, timing signoff execution, and data analysis/feedback to the PD execution team. Collaborate with methodology and CAD teams across geographies to improve closure, support timing convergence with PnR engineers, and deploy automation, dashboards, and common STA methodology to achieve first-pass silicon success.

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FursaFursa
AMD
AMD
23 hours ago

Full Chip Timing Lead

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Source: Company careers pageValidated by: Fursa AI
Last checked: 1 hour agoStatus: Live

Job Summary

Own full-chip timing closure for SoC designs, including high-frequency CPU and HBM/DDR/SerDes interfaces. Drive clock build guidance, SDC validation, timing signoff execution, and data analysis/feedback to the PD execution team. Collaborate with methodology and CAD teams across geographies to improve closure, support timing convergence with PnR engineers, and deploy automation, dashboards, and common STA methodology to achieve first-pass silicon success.
Location: Hyderabad
Workplace: Onsite
Employment Type: Full time
Job Function: Administration & Executive Assistance
Seniority: Mid level

Key Responsibilities

  • •Own full-chip timing closure and drive closure improvements for first-pass silicon success.
  • •Provide clock build guidance using multiple methods (MSCTS, Mesh) and design repeater feedback across blocks.
  • •Perform SDC analysis/validation and timing signoff execution with cross-team collaboration.
  • •Analyze data and provide feedback to the PD execution team; support timing convergence with PnR engineers.
  • •Automate signoff requirements and dashboarding, drive common STA methodology, and identify/update best practices and flow/project settings across AMD.

Pay and Benefits

Salary: INR 3,338,160 - 4,768,800 annually

Key Requirements

  • •8+ years of experience in design signoff closure, including SoC and block-level timing closure.
  • •Strong technical depth in STA and hierarchical STA for high-frequency interface closure, including multi-voltage closure.
  • •Experience with timing ECO flows, PnR and STA signoff correlation/convergence, and SDC coding/debug skills.
  • •Strong scripting experience with TCL, Perl, Python, and Makefile.
  • •Knowledge of low power physical design flows from RTL through synthesis, place and route, timing closure, and physical verification; exposure to vendor tools such as Synopsys, Cadence, and Mentor.
Experience:8+ yearsSilicon designSoCPhysical designSemiconductors
Education:Bachelor's in Computer Engineering/Electrical Engineering
Skills:CommunicationCollaborationSelf-drivingOrganizationAutomation affinity
Tech Stack:SDCSTAMSCTSMeshTCLPerlPythonMakefilePnRTiming ECOMLRTLSynthesisPlace and routePhysical verificationSynopsysCadenceMentorTileBuilder

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
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