DFT DV Engineer | 7+ years | DFT/DV/UVM/System Verilog

Work on Cisco’s Common Hardware Group to drive high-quality Design-for-Test (DFT) verification for switching, routing, and wireless silicon platforms. Create test plans and SystemVerilog/UVM test benches supporting ATE screening and in-system test/debug/diagnostics, collaborating across RTL, design-verification, and physical design teams to integrate and validate test logic through post-silicon flows. Develop reusable DFT and debug methodologies for new device models like bare die and stacked die, using tools such as DVE/Verdi and scripting with Tcl, Python, and/or Perl.