DFT DV Engineer | 7+ years | DFT/DV/UVM/System Verilog

Cisco
Bengaluru
Workplace: OnsiteFull timeFunction: Administration & Executive AssistanceExperience: 8+ yearsEducation: bachelorsSkills: ["Debugging","Solution crafting"]

Work on Cisco’s Common Hardware Group to drive high-quality Design-for-Test (DFT) verification for switching, routing, and wireless silicon platforms. Create test plans and SystemVerilog/UVM test benches supporting ATE screening and in-system test/debug/diagnostics, collaborating across RTL, design-verification, and physical design teams to integrate and validate test logic through post-silicon flows. Develop reusable DFT and debug methodologies for new device models like bare die and stacked die, using tools such as DVE/Verdi and scripting with Tcl, Python, and/or Perl.

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FursaFursa
Cisco
Cisco
1 month ago

DFT DV Engineer | 7+ years | DFT/DV/UVM/System Verilog

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Source: Company careers pageValidated by: Fursa AI
Last checked: 17 hours agoStatus: Live
Reposted: similar role first listed 1 month ago

Job Summary

Work on Cisco’s Common Hardware Group to drive high-quality Design-for-Test (DFT) verification for switching, routing, and wireless silicon platforms. Create test plans and SystemVerilog/UVM test benches supporting ATE screening and in-system test/debug/diagnostics, collaborating across RTL, design-verification, and physical design teams to integrate and validate test logic through post-silicon flows. Develop reusable DFT and debug methodologies for new device models like bare die and stacked die, using tools such as DVE/Verdi and scripting with Tcl, Python, and/or Perl.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Administration & Executive Assistance
Seniority: Mid level

Key Responsibilities

  • •Collaborate with front-end RTL and backend physical design teams to understand chip architecture and drive DFT verification.
  • •Develop thorough test planning and test benches to verify DFT architecture for ATE screening and in-system test/debug/diagnostics needs.
  • •Partner with design/design-verification and physical design teams to integrate and validate test logic across implementation and post-silicon flows.
  • •Contribute to innovative hardware DFT and test strategy for new silicon device models, including bare die and stacked die.
  • •Craft solutions and debug efficiently to support verification success.

Key Requirements

  • •Bachelor’s or Master’s Degree in Electrical or Computer Engineering with at least 8+ years of experience.
  • •Experience developing detailed test plans and test benches for DFT verification.
  • •Prior experience in testbench development using System Verilog.
  • •Debugging experience using DVE/Verdi.
  • •Scripting skills: Tcl, Python/Perl.
Experience:8+ years
Education:Bachelor's in Electrical or Computer Engineering
Skills:DebuggingSolution crafting
Tech Stack:System VerilogUVMDFTDVJTAGScan architectureMBISTBoundary scanDVEVerdiTclPythonPerlATE screeningIn-system testDiagnostics

Company Brief

Cisco
Global technology company that designs, manufactures, and sells networking hardware, telecommunications equipment, and high-technology services and products for enterprises, service providers, and governments worldwide.
Industry: Networking Equipment
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1984
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