ASIC DFT Emulation Technical Lead

Drive the DFT emulation strategy for Cisco Silicon One. Architect next-generation emulation environments, lead pre-silicon test plan execution, and validate scan, MBIST, and JTAG architectures on platforms like Palladium, Veloce, and Zebu. Partner with RTL, physical design, and ATPG teams to troubleshoot issues, ensure post-silicon pattern conversion quality, and work with emulation vendors to resolve problems across multi-terabit systems.