Design Verification Engineer
Broadcom
San Jose
Workplace: OnsiteFull timeUSD 143,800 - 230,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 12+ yearsEducation: bachelorsSkills: ["SystemVerilog","UVM","C++","Perl","Scripting"]Join Broadcom’s ASIC Product Division to perform SoC and IP verification across system and block levels. Develop verification environments with SystemVerilog and UVM, build UVM agents and behavioral models, implement coverage and assertions, and create random and directed tests while debugging simulation results.

