Design Verification Engineer

Broadcom
United States
Workplace: OnsiteFull timeUSD 143,800 - 230,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 12+ yearsEducation: bachelorsSkills: ["SystemVerilog","UVM","C++","Perl","Scripting"]

Join Broadcom’s ASIC Product Division to perform SoC and IP verification across system and block levels. Develop verification environments with SystemVerilog and UVM, build UVM agents and behavioral models, implement coverage and assertions, and create random and directed tests while debugging simulation results.

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Broadcom
Broadcom
3 months ago

Design Verification Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 33 days agoStatus: Live

Job Summary

Join Broadcom’s ASIC Product Division to perform SoC and IP verification across system and block levels. Develop verification environments with SystemVerilog and UVM, build UVM agents and behavioral models, implement coverage and assertions, and create random and directed tests while debugging simulation results.
Location: United States
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Develop verification environments and components using SystemVerilog and UVM to verify SoC and IP designs.
  • •Create UVM agents and behavioral models to support thorough verification of block and system levels.
  • •Implement coverage plans and assertions using SystemVerilog to ensure design quality.
  • •Develop random and directed test cases against specifications to exercise the design.
  • •Analyze and debug simulation failures and coverage results, collaborating with design and verification teams.

Pay and Benefits

Salary: USD 143,800 - 230,000 annually
Equity and Bonus:Equity
Perks:Health Insurance401kEquityRemote WorkPaid Leave

Key Requirements

  • •Bachelor’s degree in Electrical and Electronic Engineering, Computer Science, or equivalent
  • •12+ years of relevant industry experience preferred
  • •Experience in verifying designs at system level and block level
  • •Fluent knowledge of RTL verification methodologies including SystemVerilog
  • •Strong experience in ASIC design verification flows and DV methodologies
Experience:12+ yearsSemiconductorsASICSoC
Education:Bachelor's
Skills:SystemVerilogUVMC++PerlScripting
Tech Stack:SystemVerilogUVMC++PerlScripting

Eligibility

Work Authorization:Authorization required. Sponsorship not provided.

Company Brief

Broadcom
Designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions for the data center, networking, broadband, wireless, storage, and industrial markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Irvine, United States
Founded: 1991
WebsiteLinkedIn