Principal, IO Design Engineering

Micron Technology
Boise, Idaho
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 10+ yearsEducation: mastersSkills: ["Communication","Mentoring","Coaching","Technical analysis"]

Design and optimize high-speed IO and clocking circuits for DRAM products, including equalization and bandwidth extension. Analyze IO impairments, clock jitter, and duty error impacts to DRAM system timing budgets, and develop modeling, analysis, and simulation methods spanning circuit, full-chip, and system levels. Collaborate with product engineering, SI, process integration, and transistor modeling teams to correlate silicon performance with simulation results and support next-generation process node development.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
Micron Technology
Micron Technology
2 months ago

Principal, IO Design Engineering

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 18 hours agoStatus: Live

Job Summary

Design and optimize high-speed IO and clocking circuits for DRAM products, including equalization and bandwidth extension. Analyze IO impairments, clock jitter, and duty error impacts to DRAM system timing budgets, and develop modeling, analysis, and simulation methods spanning circuit, full-chip, and system levels. Collaborate with product engineering, SI, process integration, and transistor modeling teams to correlate silicon performance with simulation results and support next-generation process node development.
Location: Boise, Idaho
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Innovate, design, optimize, and verify high-speed IO and clocking circuits for new DRAM products.
  • •Apply high-speed circuit design techniques to improve performance evaluation of IO and clocking paths at circuit level.
  • •Develop modeling, analysis, and simulation methods to capture circuit metrics and their impact to product specs at full-chip and system level.
  • •Correlate silicon performance with simulation results by working with Product Engineering and the SI team.
  • •Collaborate with process integration and transistor modeling teams on the next process node.
  • •Analyze and address IO impairments, clock jitter, and duty error impacts to DRAM timing budgets.

Pay and Benefits

Perks:Health InsuranceDentalVisionPaid LeavePaid HolidaysParental LeaveDisability Insurance

Key Requirements

  • •MSEE with 10+ years or BSEE with 12+ years experience in analog and mixed-signal circuit design.
  • •Proficiency with UNIX and the Cadence design environment (simulation, schematic entry, SPF extraction).
  • •Understanding of device physics and basic CMOS processing techniques.
  • •Ability to supervise layout work and apply good layout practices to minimize parasitic effects.
  • •Strong communication skills to convey sophisticated technical concepts to other design peers verbally and in writing.
Experience:10+ yearsDRAMSemiconductorsHigh-speed IOAnalog and mixed-signalCircuit design
Education:Master's
Skills:CommunicationMentoringCoachingTechnical analysis
Tech Stack:UNIXCadenceSPF extractionPERLPythonAI/ML

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
Glassdoor
Glassdoor: 3.7
WebsiteLinkedIn