Lead Verification Engineer

Cadence Design Systems
Noida, Bengaluru
Workplace: OnsiteFull timeFunction: Administration & Executive AssistanceExperience: 3+ yearsEducation: mastersSkills: ["Communication","Interpersonal skills","Teamwork","Presentation","Collaboration"]

Own verification and product validation for Palladium emulation technologies, including UPF. Based in Noida/Bangalore, you’ll verify upcoming features, maintain and manage regressions, and drive quality accountability for releases. Lead technical discussions (functional specifications and test plans), review team deliverables, and mentor juniors. Improve emulation verification flows and debug design/verification issues using EDA tools.

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FursaFursa
Cadence Design Systems
Cadence Design Systems
1 day ago

Lead Verification Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 4 hours agoStatus: Live
Reposted: similar role first listed 6 months ago

Job Summary

Own verification and product validation for Palladium emulation technologies, including UPF. Based in Noida/Bangalore, you’ll verify upcoming features, maintain and manage regressions, and drive quality accountability for releases. Lead technical discussions (functional specifications and test plans), review team deliverables, and mentor juniors. Improve emulation verification flows and debug design/verification issues using EDA tools.
Location: Noida, Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Administration & Executive Assistance
Seniority: Mid level

Key Responsibilities

  • •Verify upcoming Palladium emulation features, including UPF, as part of product validation.
  • •Manage current regression sets and take full accountability for quality of Palladium releases and features.
  • •Participate in technical discussions such as Functional Specification and Testplan reviews.
  • •Review and guide team deliverables and mentor junior engineers.
  • •Contribute to improving existing emulation validation/verification flows and debug design/verification issues.

Key Requirements

  • •B.Tech/BE/M.Tech/ME with 3+ years of relevant experience in verification/validation.
  • •Strong understanding of HDLs, specifically Verilog and/or VHDL.
  • •Experience in emulation/UPF and working knowledge of EDA tools (especially Palladium) for debugging design/verification problems.
  • •Proficiency with SystemVerilog, C++, and UVM, including functional verification of complex digital systems (e.g., SoC verification).
  • •Experience with process automation using scripting and strong written, verbal, and presentation skills.
Experience:3+ yearsEmulationUPFEDA toolsSoC verificationDigital systems
Education:Master's in Electrical, Electronics or Computer Science
Skills:CommunicationInterpersonal skillsTeamworkPresentationCollaboration
Tech Stack:EmulationUPFPalladiumEDA toolsVerilogVHDLSystemVerilogC++UVMSoC verificationHDLHVLFunctional verificationRegressionsScriptingTestplan reviewsFunctional Specification reviews

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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