System Technology Research Engineer - (PhD Intern)

Intel
Santa Clara, Austin
Workplace: HybridInternshipUSD 141,998 - 142,002 annuallyFunction: Research & Scientific (R&D)Experience: 1+ yearsEducation: phdSkills: ["Analytical thinking","Problem-solving","Organizational skills","Time management","Collaboration","Stakeholder management","Adaptability","Communication"]

Develop and enhance System Technology Co-optimisation (STCO) methodologies for semiconductor and packaging technologies. Evaluate novel device and interconnect approaches, including 3D/2.5D dis-aggregation schemes using solder microbumps or hybrid bonding for memory and logic stacking across architectures. Collaborate with cross-functional teams to advance semiconductor processing and packaging roadmap technologies during a summer internship.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
Intel
Intel
2 days ago

System Technology Research Engineer - (PhD Intern)

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 6 hours agoStatus: Live

Job Summary

Develop and enhance System Technology Co-optimisation (STCO) methodologies for semiconductor and packaging technologies. Evaluate novel device and interconnect approaches, including 3D/2.5D dis-aggregation schemes using solder microbumps or hybrid bonding for memory and logic stacking across architectures. Collaborate with cross-functional teams to advance semiconductor processing and packaging roadmap technologies during a summer internship.
Location: Santa Clara, Austin
Workplace: Hybrid
Employment Type: Internship
Job Function: Research & Scientific (R&D)
Seniority: Intern level

Key Responsibilities

  • •Develop and enhance STCO methodologies for semiconductor and packaging technologies.
  • •Perform system-level evaluations of novel devices, interconnects, patterning, materials, systems, and integration schemes.
  • •Evaluate 3D/2.5D dis-aggregation approaches using solder microbumps or hybrid bonding for memory and logic stacking.
  • •Collaborate with diverse teams to drive innovation across different product architectures.

Pay and Benefits

Salary: USD 141,998 - 142,002 annually
Equity and Bonus:Equity
Perks:Health InsuranceRetirementPaid Leave

Key Requirements

  • •Active Ph.D. candidacy in Electrical Engineering, Electronics Engineering, Computer Architecture and Design, or a related field.
  • •1-2+ years of research experience in areas such as system architecture modeling, digital circuit analysis/design, VLSI physical layout, EDA, or multi-physics modeling.
  • •Familiarity with IC design and physical layout tools such as Cadence Virtuoso or Synopsis Fusion Compiler.
  • •Strong analytical and problem-solving skills to tackle complex challenges with a strategic approach.
  • •Ability to communicate effectively and collaborate with diverse teams.
Experience:1+ years
Education:PhD / Doctorate in Electrical Engineering; Electronics Engineering; Computer Architecture and Design
Skills:Analytical thinkingProblem-solvingOrganizational skillsTime managementCollaborationStakeholder managementAdaptabilityCommunication
Tech Stack:PythonCadence VirtuosoSynopsis Fusion Compiler

Company Brief

Intel
Designs and manufactures semiconductor chips, processors, and related hardware for PCs, data centers, networking, and embedded applications, while providing software and services to accelerate computing across industries globally.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1968
Glassdoor
Glassdoor: 3.8
WebsiteLinkedInGlassdoor