Staff SOC DFX RTL Design Engineer

AMD
Penang
Workplace: HybridFull timeMYR 126,000 - 180,000 annuallyFunction: Design (Product/UX/UI/Visual)Education: bachelorsSkills: ["Communication","Analytical thinking","Problem-solving","Collaboration","Teamwork"]

Own RTL DFX design integration and edge-cutting DFX feature planning/implementation for next-generation microprocessors. Partner with architecture, IP, physical design, and cross-site verification teams to achieve first-pass silicon success, including DFT RTL insertion, synthesis, equivalency checking, static timing support, and DFx logic verification. Provide bring-up and pattern debug support during first silicon qualification and failure analysis using industry DFT/EDA tools and simulation/debug workflows.

Loading

Loading job details...

Preparing the role view and application actions.

FursaFursa
AMD
AMD
4 hours ago

Staff SOC DFX RTL Design Engineer

✓ Verified Job

Canonical indexed version, validated from employer's careers page.

Source: Company careers pageValidated by: Fursa AI
Last checked: 1 hour agoStatus: Live

Job Summary

Own RTL DFX design integration and edge-cutting DFX feature planning/implementation for next-generation microprocessors. Partner with architecture, IP, physical design, and cross-site verification teams to achieve first-pass silicon success, including DFT RTL insertion, synthesis, equivalency checking, static timing support, and DFx logic verification. Provide bring-up and pattern debug support during first silicon qualification and failure analysis using industry DFT/EDA tools and simulation/debug workflows.
Location: Penang
Workplace: Hybrid
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Plan and implement DFX features such as JTAG, scan, boundary scan, and debug features.
  • •Collaborate with CAD and IP teams on DFX requirements, implementation, and power scenarios.
  • •Work with DFX verification teams to ensure quality and verification of DFx logic.
  • •Participate in DFX initiatives and process development, supporting cross-functional teams with technical guidance.
  • •Perform DFT RTL design integration, insertion, synthesis, equivalency checking, timing analysis, and provide bring-up/pattern debug support during first silicon qualification and failure analysis.

Pay and Benefits

Salary: MYR 126,000 - 180,000 annually

Key Requirements

  • •Knowledge of DFT techniques such as JTAG/IEEE standards, SSN, Scan and ATPG, and memory/logic BIST/repair concepts.
  • •Experience debugging RTL and gate-level simulations using Verilog simulator and waveform debugging tools.
  • •Hands-on experience with DFT tooling such as Mentor TestKompress and/or Synopsys Tetramax/DFTMAX.
  • •Familiarity with Verilog/SystemVerilog and DFX RTL design integration tasks including insertion, synthesis, equivalency checking, timing analysis, and constraints definition.
  • •Comfort with scripting (Perl/Shell, Python, TCL and other languages) and low-power DFX implementation experience.
Education:Bachelor's in Computer engineering/Electrical Engineering
Skills:CommunicationAnalytical thinkingProblem-solvingCollaborationTeamwork
Languages:English
Tech Stack:JTAGIEEE standardsSSNScanATPGMemory BISTLogic BISTDFTDFXVerilogSystemVerilogVCSVerilog simulatorWaveform debuggingMentor TestKompressSynopsys TetramaxDFTMAXPerlShell scriptingPython

Company Brief

AMD
Designs and produces semiconductor products including CPUs, GPUs, and adaptive SoCs for consumer, enterprise, and embedded markets, competing across PCs, data centers, and gaming industries.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Santa Clara, United States
Founded: 1969
Glassdoor
Glassdoor: 3.9
WebsiteLinkedIn