ASIC Physical Design Engineer

Lead macro-level RTL-to-GDSII physical implementation and signoff for complex SoC/block projects. Collaborate with Front-End teams to translate architecture into physical design, performing synthesis, floorplanning, placement, CTS, and routing while optimizing power, performance, and area. Execute STA, physical verification, signoff closure, and address EM/IR drop issues to ensure reliable silicon. Hybrid role with four days at the Yerevan office.