Sr Principal Design Engineer

Cadence Design Systems
Cork, Munich, Edinburgh
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 15+ yearsEducation: bachelorsSkills: ["Technical leadership","Problem-solving","Technical communication","Planning","Mentoring"]

Provide hands-on technical leadership for complex, high-visibility silicon programs spanning synthesis/netlist through physical implementation, signoff, and tapeout. Drive advanced methodologies to achieve aggressive PPA targets, collaborate with PSG and Cadence R&D to close product/tool gaps, and lead investigations into silicon failures and convergence issues. Mentor implementation engineers and represent Cadence as a technical thought leader with strategic customers across EMEA.

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Cadence Design Systems
Cadence Design Systems
12 hours ago

Sr Principal Design Engineer

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Last checked: 12 hours agoStatus: Live

Job Summary

Provide hands-on technical leadership for complex, high-visibility silicon programs spanning synthesis/netlist through physical implementation, signoff, and tapeout. Drive advanced methodologies to achieve aggressive PPA targets, collaborate with PSG and Cadence R&D to close product/tool gaps, and lead investigations into silicon failures and convergence issues. Mentor implementation engineers and represent Cadence as a technical thought leader with strategic customers across EMEA.
Location: Cork, Munich, Edinburgh
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Provide technical leadership for complex silicon programs from synthesis/netlist through physical implementation, signoff, and tapeout.
  • •Develop and deploy advanced methodologies to meet aggressive PPA (power, performance, area) objectives.
  • •Collaborate with PSG and Cadence R&D to identify product gaps, influence tool development, and drive enhancements for advanced silicon designs.
  • •Drive technical innovation across physical design, timing, power, signal integrity, physical verification, and signoff with the PSG European team.
  • •Lead technical investigations for silicon failures and convergence issues, establish reusable methodologies, and mentor implementation engineers as a technical authority.

Key Requirements

  • •Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related discipline.
  • •15+ years of relevant semiconductor engineering experience or equivalent technical achievement.
  • •Proven tape-out experience on advanced process nodes.
  • •Deep expertise in semiconductor implementation flow and the SoC development lifecycle, including process technologies and physical implementation challenges.
  • •Experience developing and delivering complex semiconductor products and working across functional boundaries; experience working with semiconductor customers, foundries, or technology partners.
Experience:15+ years
Education:Bachelor's
Skills:Technical leadershipProblem-solvingTechnical communicationPlanningMentoring
Languages:English
Tech Stack:Silicon implementationAdvanced EDASynthesisNetlistPhysical implementationSignoffTapeoutPPATiming closurePower optimisationSignal integrityElectromigrationRTL-to-GDSIIGDSIISoC integrationHierarchical implementationIP integrationProcess/design technology co-optimizationDTCOAdvanced packaging

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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Glassdoor: 3.9
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