Sr Principal Design Engineer

Cadence Design Systems
Bengaluru
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 10-15 yearsSkills: ["Communication","Collaboration","Problem-solving"]

Lead DFT ownership for projects, defining test architectures, RTL changes for DFT, and verification across scan, iJTAG, and boundary scan; develop timing constraints for test modes; collaborate with customers and Marketing/Pre-Sales; support post-silicon bring-up; work on high-speed, low-power designs in Cadence's advanced hardware/EDA environment.

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FursaFursa
Cadence Design Systems
Cadence Design Systems
6 months ago

Sr Principal Design Engineer

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Source: Company careers pageValidated by: Fursa AI
Last checked: 2 hours agoStatus: Live
Reposted: similar role first listed 9 months ago

Job Summary

Lead DFT ownership for projects, defining test architectures, RTL changes for DFT, and verification across scan, iJTAG, and boundary scan; develop timing constraints for test modes; collaborate with customers and Marketing/Pre-Sales; support post-silicon bring-up; work on high-speed, low-power designs in Cadence's advanced hardware/EDA environment.
Location: Bengaluru
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)

Key Responsibilities

  • •Own DFT for projects including test architecture definition and RTL changes for DFT.
  • •Performing scan insertion, LEC checks, and low power CLP checks.
  • •Developing timing constraints for test mode timing closure.
  • •ATPG and boundary scan, ACJTAG, IEEE 1500 implementation and verification.
  • •IEEE1687 (iJTAG) compliant ICL/PDL for functional manufacturing tests; run zero delay and timing simulations and debugging; support post-silicon bring up and interact with customers and Marketing/Pre-Sales.

Key Requirements

  • •Experience: 10-15 years
  • •DFT ownership of projects including test architecture definition and RTL changes for DFT
  • •Experience with scan insertion, LEC checks, and low power CLP checks
  • •Developing timing constraints for test mode timing closure
  • •IEEE1687 (iJTAG) compliant ICL/PDL for functional manufacturing tests
Experience:10-15 yearsSemiconductorsEDAHardware design
Skills:CommunicationCollaborationProblem-solving
Tech Stack:DFTRTLATPGLECIEEE 1687IJTAGBoundary scanACJTAG

Company Brief

Cadence Design Systems
Provides electronic design automation (EDA) software, IP, and services for semiconductor and systems companies to design, verify, and implement integrated circuits, systems-on-chip, and electronic systems across industries including communications, automotive, and consumer electronics.
Industry: Developer Tools
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: San Jose, United States
Founded: 1988
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