Semiconductor Principal Design Engineer

Micron Technology
Tokyo
Workplace: OnsiteFull timeFunction: Design (Product/UX/UI/Visual)Experience: 8+ yearsEducation: mastersSkills: ["Technical leadership","Cross-functional communication","Project planning","Design trade-off evaluation","Debug and correlation"]

Design and optimize datapath circuits for NAND flash memory, focusing on TSV (Through-Silicon Via) interface architecture, signal/power integrity, and DFT validation. Lead technical design projects by planning, laying out, and verifying TSV interfaces and wide internal parallel buses to achieve timing closure under PVT variations. Drive architectural decisions, interface with process/DTCO, packaging, and cross-functional teams, and support post-silicon debug and tape-out revisions.

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FursaFursa
Micron Technology
Micron Technology
3 months ago

Semiconductor Principal Design Engineer

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Job Summary

Design and optimize datapath circuits for NAND flash memory, focusing on TSV (Through-Silicon Via) interface architecture, signal/power integrity, and DFT validation. Lead technical design projects by planning, laying out, and verifying TSV interfaces and wide internal parallel buses to achieve timing closure under PVT variations. Drive architectural decisions, interface with process/DTCO, packaging, and cross-functional teams, and support post-silicon debug and tape-out revisions.
Location: Tokyo
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Mid level

Key Responsibilities

  • •Design and optimize TSV interface circuits (Rx/Tx) for internal TSV channels, including impedance matching and timing margin analysis.
  • •Define and implement signal integrity and power integrity requirements for TSV channels and highly parallel IO/array operations.
  • •Develop and verify TSV-specific DFT circuits (loopback modes, continuity checks, lane redundancy/remapping) and execute functional verification using full chip simulation and Verilog regression.
  • •Architect the internal parallel datapath and clocking/synchronization strategy (data line sense amplifier, redundancy logic, bus driver, TSV output interface; clock distribution and skew management) to achieve timing closure.
  • •Support post-silicon validation and debug by correlating results, driving tape-out revisions, and coordinating with process technology/DTCO, packaging/assembly, and integration teams.

Key Requirements

  • •BS or MS in Electrical Engineering with 8+ years of relevant memory circuit design experience, preferably DRAM, NAND, or high-density memory technologies.
  • •Experience designing TSV (Through-Silicon Via) interface circuits or high-speed memory interfaces, including timing analysis, parasitic modeling, and signal integrity.
  • •Advanced understanding of highly parallel bus performance with power and area optimization, including clock distribution and skew management; EpB (Energy per Bit) optimization in 3D-stacked memory architectures.
  • •Ability to manage complex circuit design projects across multiple functional blocks and cross-functional teams, communicating design trade-offs, progress, and technical outcomes.
  • •Experience with highly parallel IO/array operations and the power/PDN considerations tied to wide datapath performance.
Experience:8+ yearsMemory circuit designDRAMNANDHigh-density memory3D-stacked memoryHBM
Education:Master's in Electrical Engineering
Skills:Technical leadershipCross-functional communicationProject planningDesign trade-off evaluationDebug and correlation
Tech Stack:TSVNAND flashDRAMVerilogDFTPDNBSIMHBM3HBM3EHBM4HBMDDR4DDR5LPDDR4LPDDR5LPDDR6NV-LPDDR4PVT variationsEye margin analysisCrosstalk analysis

Company Brief

Micron Technology
Designs and manufactures semiconductor memory and storage solutions, including DRAM, NAND, and NOR flash, for computing, networking, mobile, and automotive markets worldwide.
Industry: Electronics Manufacturing
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Public Company
Valuation: Public Company (Market Cap in USD)
Funding: IPO / Publicly Listed
Headquarters: Boise, United States
Founded: 1978
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