Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

Lead partition synthesis and physical implementation for ASIC/SoC designs, driving timing, power and area targets while developing design methodologies and automation. Collaborate with cross-disciplinary teams to optimize RTL/design tradeoffs, resolve timing and congestion issues, and ensure signoff in STA, noise, and physical verification. Requires a Bachelor’s in an engineering field and 5+ years in ASIC/physical design.