Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

SpaceX
Irvine, Austin, Sunnyvale
Workplace: OnsiteFull timeUSD 160,000 - 220,000 annuallyFunction: Design (Product/UX/UI/Visual)Experience: 5+ yearsEducation: bachelorsSkills: ["Problem-solving","Collaboration","Self-motivated","Detail-oriented","Communication"]

Lead partition synthesis and physical implementation for ASIC/SoC designs, driving timing, power and area targets while developing design methodologies and automation. Collaborate with cross-disciplinary teams to optimize RTL/design tradeoffs, resolve timing and congestion issues, and ensure signoff in STA, noise, and physical verification. Requires a Bachelor’s in an engineering field and 5+ years in ASIC/physical design.

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FursaFursa
SpaceX
SpaceX
4 months ago

Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

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Job Summary

Lead partition synthesis and physical implementation for ASIC/SoC designs, driving timing, power and area targets while developing design methodologies and automation. Collaborate with cross-disciplinary teams to optimize RTL/design tradeoffs, resolve timing and congestion issues, and ensure signoff in STA, noise, and physical verification. Requires a Bachelor’s in an engineering field and 5+ years in ASIC/physical design.
Location: Irvine, Austin, Sunnyvale
Workplace: Onsite
Employment Type: Full time
Job Function: Design (Product/UX/UI/Visual)
Seniority: Sr. Manager level

Key Responsibilities

  • •Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
  • •Develop/improve physical design methodologies and automation scripts for various implementation steps
  • •Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
  • •Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
  • •Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

Pay and Benefits

Salary: USD 160,000 - 220,000 annually
Equity and Bonus:Equity
Perks:MedicalVisionDental401kEquityParental LeavePaid LeaveDisability Insurance

Key Requirements

  • •Bachelor’s degree in electrical engineering, computer engineering or computer science
  • •5+ years of ASIC and/or physical design flow development experience in industry
  • •Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
  • •Strong experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
  • •Knowledge of deep sub-micron FinFET and CMOS solid state physics
Experience:5+ yearsASICSiliconSemiconductorPhysical design
Education:Bachelor's
Skills:Problem-solvingCollaborationSelf-motivatedDetail-orientedCommunication
Languages:English
Tech Stack:PythonTCLPerlBashMakefileRTL2GDSIISTADFTMBISTLBIST

Company Brief

SpaceX
Designs, manufactures, and launches advanced rockets and spacecraft for commercial and government customers, aiming to reduce space transportation costs and enable human life on Mars through reusable launch vehicles and integrated space systems.
Industry: Aerospace Manufacturing
Company Size: Enterprise (1,001+ employees)
Growth: Established Company
Valuation: Hectocorn (USD 100B+)
Funding: Series E+
Headquarters: Hawthorne, United States
Founded: 2002
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