Synthesis & STA Engineer -Singapore

ByteDance
Singapore
Workplace: OnsiteFull timeFunction: Product ManagementSkills: []

Own logic synthesis and timing closure for chip architectures and RTLs, including SDC preparation, hierarchical/full-chip STA signoff, and power-aware constraint tuning. Implement low-power techniques using UPF, clock/power gating, and dynamic voltage scaling, while partnering with front-end and backend teams on architectural exploration and floorplanning/P&R. Drive formal verification and equivalence checking with tools such as Conformal and Formality.

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FursaFursa
ByteDance
ByteDance
1 month ago

Synthesis & STA Engineer -Singapore

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Source: Company careers pageValidated by: Fursa AI
Last checked: 29 days agoStatus: Live
Reposted: similar role first listed 1 month ago

Job Summary

Own logic synthesis and timing closure for chip architectures and RTLs, including SDC preparation, hierarchical/full-chip STA signoff, and power-aware constraint tuning. Implement low-power techniques using UPF, clock/power gating, and dynamic voltage scaling, while partnering with front-end and backend teams on architectural exploration and floorplanning/P&R. Drive formal verification and equivalence checking with tools such as Conformal and Formality.
Location: Singapore
Workplace: Onsite
Employment Type: Full time
Job Function: Product Management
Seniority: Mid level

Key Responsibilities

  • •Perform logic synthesis and optimize designs for architectures and RTLs.
  • •Prepare and tune timing constraints (SDC) and run hierarchical/full-chip STA signoff for timing closure.
  • •Implement low-power design techniques and constraints using UPF, clock gating, power gating, and dynamic voltage scaling.
  • •Conduct formal verification and equivalence checking using Conformal and Formality.
  • •Collaborate with front-end and backend engineers on architectural exploration, floorplanning, place & route (P&R), congestion analysis, and timing bottlenecks.

Key Requirements

  • •3+ years of IC design experience focused on SDC, synthesis, timing signoff, low-power implementation, and power optimization.
  • •Proficiency in Verilog/SystemVerilog for RTL-to-GDSII flows.
  • •Experience with EDA tools including Fusion Compiler, Genus/Innovus+, and PrimeTime/Tempus.
  • •Bachelor’s or Master’s degree in electrical engineering, computer engineering, or a related field.
  • •Working knowledge of timing analysis and multi-clock domain handling, plus familiarity with DFT methodologies (scan, bscan, mbist).
Experience:IC design
Education:
Tech Stack:Logic SynthesisDesign for Testability (DFT)Static Timing Analysis (STA)SDCUPFClock gatingPower gatingDynamic voltage scalingVerilogSystemVerilogRTL-to-GDSIIFusion CompilerGenusInnovus+PrimeTimeTempusFormalityConformal LPConformalFormal verification

Company Brief

ByteDance
Develops consumer internet and content platforms, including TikTok and other apps for short-form video, news, and entertainment. It also builds advertising, commerce, and creator tools that connect audiences, brands, and publishers across global markets.
Industry: Digital Media
Company Size: Enterprise (1,001+ employees)
Revenue: USD 1B+
Growth: Established Company
Headquarters: Beijing, China
Founded: 2012
WebsiteLinkedIn